Chapter 3 - MACSI Host Interface

A value between 1 and 0x20 (40 decimal) causes the controller, after being granted the bus, to transfer data until 1) there is no more data, or 2) 16 micro seconds elapses, or 3) one of the bus request lines on the VMEbus is asserted.

With a value between 0x21 and 0x80, the controller, after being granted the bus, will transfer data until 1) there is no more data to be transferred, or 2) 32 microseconds elapses.

With a value greater than 0x80, the controller will, after being granted the bus, transfer data until 1) there is no more data, or 2) 64 microseconds elapses.

Offboard CRB DMA Transfer Control Word

This work defines the DMA transfer of returned commands from the controller to the host, using the field definition found in the Common IOPB Structures definition.

Offboard CRB host address

These two fields contain the address in host memory to which the controller will post off-board Command response blocks. If these fields are zero, responses will be posted via on-board space only. When posting to the offboard location, the controller will DMA transfer the 208 bytes of memory contents starting at the beginning of the Command Response Block through the end of Short I/O. The host needs to make sure that adequate memory is mapped and available for this transfer.

When the controller sets the CRBV in the onboard space, this signals the contents of both the offboard and onboard CRB location are valid. When the host clears the CRBV bit, the controller will assume that the offboard location is available to write the next response.

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