Chapter 1 - Introduction

Ethernet Front End Channel (FEC)

The 82596CA® Local Area Network (LAN) Co-processor is used as the FEC Ethernet controller. The 82596CA® communicates with the rest of the board through the LBUS. The 82596CA® has a 80486® type bus interface, which requires two PALs to convert the 80486® interface to meet the LBUS (MC68040_ type) specification. The 82596CA® can be a master or a slave of the LBUS. As a LBUS master, the 82596CA® accesses both data and command lists for both transmits and receives commands. As a slave, the CPU has write access to four locations within the 82596CA® to establish a software reset or initialization and reset test pointers.

To complete the connections to the Ethernet cable, the 82596CA® connects to the encoder/decoder interface device (82503®) which in turn connects through analog circuitry to the cable connectors. The encoder/decoder and analog circuitry provides support for both 10BaseT and the Attachment Unit Interface (AUI).

VMEbus Master Interface

The VMEbus Master Interface consists of a VLSI DMA engine and the required high current VMEbus driver and receiver devices.

DMA Engine

The DMA engine interfaces the LBUS with the VMEbus and performs the LBUS to VMEbus DMA functions. The DMA engine communicates with the rest of the board through the LBUS. The DMA engine can be a master and a slave of the LBUS. As a LBUS master, the DMA engine accesses linked list DMA commands as well as buffered data. As a LBUS slave, the DMA engine is accessed by the CPU for configuration and status information.

The DMA engine provides the VMEbus interrupter support logic, some of the internal CPU interrupts (with vectors) and the board timers.

The DMA engine also provides many functions and features which are not currently used on the Condor board. These functions include a non-DMA LBUS to VMEbus interface, VMEbus slave to LBUS interface, system controller functions, an interrupt handler and several global general purpose registers.

VMEbus Drivers And Receivers

External buffers are used to provide a more isolated and robust interface to the VMEbus. These buffers drive and receive most of the VMEbus data, address and control lines.

Local Bus

The Local Bus (LBUS) is based primarily upon a MC68040® CPU bus structure. The channels and functions connected to the LBUS must conform to the MC68040_bus specification. This allows easy design and development of a wide variety of front ends and back ends into the controller board.

The LBUS encompasses the actual bus itself, the buffer memory and all of the logic which is not associated with any one particular channel (front end or back end) on the LBUS.

The buffer memory is configured as two SRAM banks which consists of four SRAM devices for each bank. The two banks of SRAM combined provide for 128K-, 256K-, 512K- and 1M-byte of memory.

The LBUS logic consists of an arbiter, an address decoder, a burst mode address counter, a write strobe generator, a transfer acknowledge generator, a SRAM buffer memory and any miscellaneous handshake logic required to connect the channels to the LBUS.

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