
Chapter 3 - MACSI Host Interface
Controller Initialization Block (CIB)
The CIB contains the actual values to use when initializing the controller. It may be located anywhere in Short I/O, though it makes sense to place it after the MCE and before the Command Response Block.
Table
Controller Initialization Block
Offst | 15 | 14 |
| 13 | 12 | 11 |
| 10 |
| 9 |
| 8 |
| 7 |
| 6 | 5 | 4 | 3 | 2 |
| 1 | 0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |||||||||
0x00 |
|
|
|
| Reserved |
|
|
|
|
|
| Number of CQE Entries |
|
| |||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| ||||||
0x01 |
|
|
|
|
|
|
| Special Network Options |
|
|
|
|
|
|
| ||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| ||
0x02 |
|
|
|
|
|
|
|
|
|
| Reserved |
|
|
|
|
|
|
|
|
|
| ||
|
|
|
|
|
|
|
|
|
|
|
|
|
| ||||||||||
0x03 |
|
|
|
|
| Ethernet Physical Address (Port 0) |
|
|
|
|
|
|
| ||||||||||
to |
|
|
|
|
|
|
|
|
|
| (6 Bytes) |
|
|
|
|
|
|
|
|
|
| ||
0x05 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| ||||||||||
0x06 |
|
|
|
|
| Ethernet Physical Address (Port 1) |
|
|
|
|
|
|
| ||||||||||
to |
|
|
|
|
|
|
|
|
|
| (6 Bytes) |
|
|
|
|
|
|
|
|
|
| ||
0x08 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| ||||||||||
0x09 |
|
|
|
|
| Ethernet Physical Address (Port 2) |
|
|
|
|
|
|
| ||||||||||
to |
|
|
|
|
|
|
|
|
|
| (6 Bytes) |
|
|
|
|
|
|
|
|
|
| ||
0x0B |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| ||||||||||
0x0C |
|
|
|
|
| Ethernet Physical Address (Port 3) |
|
|
|
|
|
|
| ||||||||||
to |
|
|
|
|
|
|
|
|
|
| (6 Bytes) |
|
|
|
|
|
|
|
|
|
| ||
0x0E |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |||||||
0x0F |
| Controller Completion Level |
|
|
|
|
|
| Controller Completion Vector |
|
| ||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
| |||||||||||
0x10 |
|
| Controller Error Level |
|
|
|
|
|
| Controller Error Vector |
|
| |||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |||
0x11 |
|
|
|
|
|
|
|
|
| DMA Burst Count |
|
|
|
|
|
|
|
| |||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| ||
0x12 |
|
|
|
|
|
|
|
|
|
| Reserved |
|
|
|
|
|
|
|
|
|
| ||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| ||||||||
0x13 |
|
|
|
|
|
|
| Offboard CRB Transfer Word |
|
|
|
|
|
|
| ||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
| ||||||||||
0x14 |
|
|
|
|
|
| Offboard CRB Host Address (MSW) |
|
|
|
|
|
| ||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
| ||||||||||
0x15 |
|
|
|
|
|
| Offboard CRB Host Address (LSW) |
|
|
|
|
|
| ||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
This field specifies the number of Command Queue entries to be used in the circular queue. Without using offboard IOPBs, the maximum number ranges between 30 and 37. With offboard CQEs, this number can be increased to 151 (1812 / 12). Choosing the correct value is important to ensure maximum performance of the controller.
74