NXP Semiconductors UM10310 21. Tables

User manual Rev. 01 — 1 December 2008 135 of 139

NXP Semiconductors UM10310

P89LPC9321 User manual

21. Tables

Table 1. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table 2. Special function registers. . . . . . . . . . . . . . . . . 11

Table 3. Extended special function registers[1] . . . . . . .19

Table 4. Data RAM arrangement . . . . . . . . . . . . . . . . . .21

Table 5. On-chip RC oscillator trim register (TRIM -

address 96h) bit allocation . . . . . . . . . . . . . . . .22

Table 6. On-chip RC oscillator trim register (TRIM -

address 96h) bit description . . . . . . . . . . . . . .23

Table 7. Clock control register (CLKCON - address

FFDEh) bit allocation . . . . . . . . . . . . . . . . . . . .24

Table 8. Clock control register (CLKCON - address

FFDEh) bit description . . . . . . . . . . . . . . . . . . .24

Table 9. Oscillator type selection for clock switch . . . . .25

Table 10. Interrupt priority level . . . . . . . . . . . . . . . . . . . .26

Table 11. Summary of interrupts . . . . . . . . . . . . . . . . . . .27

Table 12. Number of I/O pins available . . . . . . . . . . . . . .28

Table 13. Port output configuration settings . . . . . . . . . .29

Table 14. Port output configuration . . . . . . . . . . . . . . . . .32

Table 15. BOD Trip points configuration. . . . . . . . . . . . . .34

Table 16. BOD Reset and BOD Interrupt configuration . .34

Table 17. Power reduction modes . . . . . . . . . . . . . . . . . .35

Table 18. Power Control register (PCON - address 87h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 19. Power Control register (PCON - address 87h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 20. Power Control register A (PCONA - address B5h)

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 21. Power Control register A (PCONA - address B5h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 22. Reset Sources register (RSTSRC - address DFh)

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Table 23. Reset Sources register (RSTSRC - address DFh)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .38

Table 24. Timer/Counter Mode register (TMOD - address

89h) bit allocation . . . . . . . . . . . . . . . . . . . . . .39

Table 25. Timer/Counter Mode register (TMOD - address

89h) bit description . . . . . . . . . . . . . . . . . . . . .39

Table 26. Timer/Counter Auxiliary Mode register (TAMOD -

address 8Fh) bit allocation . . . . . . . . . . . . . . .40

Table 27. Timer/Counter Auxiliary Mode register (TAMOD -

address 8Fh) bit description . . . . . . . . . . . . . .40

Table 28. Timer/Counter Control register (TCON) - address

88h) bit allocation . . . . . . . . . . . . . . . . . . . . . .41

Table 29. Timer/Counter Control register (TCON - address

88h) bit description . . . . . . . . . . . . . . . . . . . . .41

Table 30. Real-time Clock/System Timer clock sources .45

Table 31. Real-time Clock Control register (RTCCON -

address D1h) bit allocation . . . . . . . . . . . . . . .46

Table 32. Real-time Clock Control register (RTCCON -

address D1h) bit description . . . . . . . . . . . . . .47

Table 33. CCU prescaler control register, high byte

(TPCR2H - address CBh) bit allocation . . . . . .49

Table 34. CCU prescaler control register, high byte

(TPCR2H - address CBh) bit description . . . . .49

Table 35. CCU prescaler control register, low byte (TPCR2L

- address CAh) bit allocation . . . . . . . . . . . . . .49

Table 36. CCU prescaler control register, low byte (TPCR2L

- address CAh) bit description . . . . . . . . . . . . . 49

Table 37. CCU control register 0 (TCR20 - address C8h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Table 38. CCU control register 0 (TCR20 - address C8h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Table 39. Capture compare control register (CCRx -

address Exh) bit allocation . . . . . . . . . . . . . . .51

Table 40. Capture compare control register (CCRx -

address Exh) bit description . . . . . . . . . . . . . .51

Table 41. Event delay counter for input capture . . . . . . . 52

Table 42. Output compare pin behavior. . . . . . . . . . . . . . 54

Table 43. CCU control register 1 (TCR21 - address F9h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Table 44. CCU control register 1 (TCR21 - address F9h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Table 45. CCU interrupt status encode register (TISE2 -

address DEh) bit allocation . . . . . . . . . . . . . . .57

Table 46. CCU interrupt status encode register (TISE2 -

address DEh) bit description . . . . . . . . . . . . . .57

Table 47. CCU interrupt flag register (TIFR2 - address E9h)

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .58

Table 48. CCU interrupt flag register (TIFR2 - address E9h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .58

Table 49. CCU interrupt control register (TICR2 - address

C9h) bit allocation . . . . . . . . . . . . . . . . . . . . . .58

Table 50. CCU interrupt control register (TICR2 - address

C9h) bit description . . . . . . . . . . . . . . . . . . . . .58

Table 51. UART SFR addresses . . . . . . . . . . . . . . . . . . .60

Table 52. UART baud rate generation . . . . . . . . . . . . . . 60

Table 53. Baud Rate Generator Control register (BRGCON

- address BDh) bit allocation . . . . . . . . . . . . . .61

Table 54. Baud Rate Generator Control register (BRGCON

- address BDh) bit description . . . . . . . . . . . . . 61

Table 55. Serial Port Control register (SCON - address 98h)

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .62

Table 56. Serial Port Control register (SCON - address 98h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .62

Table 57. Serial Port modes . . . . . . . . . . . . . . . . . . . . . . 62

Table 58. Serial Port Status register (SSTAT - address BAh)

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .62

Table 59. Serial Port Status register (SSTAT - address BAh)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .63

Table 60. FE and RI when SM2 = 1 in Modes 2 and 3 . . 66

Table 61. Slave 0/1 examples . . . . . . . . . . . . . . . . . . . . .69

Table 62. Slave 0/1/2 examples . . . . . . . . . . . . . . . . . . .69

Table 63. I2C data register (I2DAT - address DAh) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Table 64. I2C slave address register (I2ADR - address DBh)

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .71

Table 65. I2C slave address register (I2ADR - address DBh)

bit description. . . . . . . . . . . . . . . . . . . . . . . . . .71

Table 66. I2C Control register (I2CON - address D8h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Table 67. I2C Control register (I2CON - address D8h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .72