NXP Semiconductors UM10310 22. Figures

User manual Rev. 01 — 1 December 2008 137 of 139

NXP Semiconductors UM10310

P89LPC9321 User manual

22. Figures

Fig 1. TSSOP28 pin configuration. . . . . . . . . . . . . . . . . .3

Fig 2. PLCC28 pin configuration . . . . . . . . . . . . . . . . . . .4

Fig 3. DIP28 pin configuration. . . . . . . . . . . . . . . . . . . . .4

Fig 4. Functional diagram . . . . . . . . . . . . . . . . . . . . . . . .8

Fig 5. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Fig 6. P89LPC9321 memory map. . . . . . . . . . . . . . . . .20

Fig 7. Using the crystal oscillator. . . . . . . . . . . . . . . . . .23

Fig 8. Block diagram of oscillator control. . . . . . . . . . . .24

Fig 9. Interrupt sources, interrupt enables, and

power-down wake-up sources. . . . . . . . . . . . . . .28

Fig 10. Quasi-bidirectional output.. . . . . . . . . . . . . . . . . .30

Fig 11. Open drain output.. . . . . . . . . . . . . . . . . . . . . . . .30

Fig 12. Input only.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Fig 13. Push-pull output. . . . . . . . . . . . . . . . . . . . . . . . . .31

Fig 14. Block diagram of reset. . . . . . . . . . . . . . . . . . . . .38

Fig 15. Timer/counter 0 or 1 in Mode 0 (13-bit counter).. 42

Fig 16. Timer/counter 0 or 1 in mode 1 (16-bit counter).. 42

Fig 17. Timer/counter 0 or 1 in Mode 2

(8-bit auto-reload).. . . . . . . . . . . . . . . . . . . . . . . .42

Fig 18. Timer/counter 0 Mode 3 (two 8-bit counters). . . .43

Fig 19. Timer/counter 0 or 1 in mode 6

(PWM auto-reload).. . . . . . . . . . . . . . . . . . . . . . .43

Fig 20. Real-time clock/system timer block diagram.. . . .44

Fig 21. Capture Compare Unit block diagram.. . . . . . . . .48

Fig 22. Asymmetrical PWM, downcounting. . . . . . . . . . . 53

Fig 23. Symmetrical PWM. . . . . . . . . . . . . . . . . . . . . . . .53

Fig 24. Alternate output mode. . . . . . . . . . . . . . . . . . . . .54

Fig 25. Capture/compare unit interrupts.. . . . . . . . . . . . .57

Fig 26. Baud rate generation for UART (Modes 1, 3) . . .61

Fig 27. Serial Port Mode 0 (double buffering must be

disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Fig 28. Serial Port Mode 1 (only single transmit buffering

case is shown). . . . . . . . . . . . . . . . . . . . . . . . . . .65

Fig 29. Serial Port Mode 2 or 3 (only single transmit

buffering case is shown) . . . . . . . . . . . . . . . . . . .65

Fig 30. Transmission with and without double buffering .67

Fig 31. I2C-bus configuration. . . . . . . . . . . . . . . . . . . . . .71

Fig 32. Format in the Master Transmitter mode. . . . . . . .75

Fig 33. Format of Master Receiver mode.. . . . . . . . . . . .76

Fig 34. A Master Receiver switches to Master Transmitter

after sending Repeated Start. . . . . . . . . . . . . . . .76

Fig 35. Format of Slave Receiver mode.. . . . . . . . . . . . .77

Fig 36. Format of Slave Transmitter mode.. . . . . . . . . . .77

Fig 37. I2C serial interface block diagram.. . . . . . . . . . . .78

Fig 38. SPI block diagram.. . . . . . . . . . . . . . . . . . . . . . . .85

Fig 39. SPI single master single slave configuration. . . . 87

Fig 40. SPI dual device configuration, where either can be a

master or a slave. . . . . . . . . . . . . . . . . . . . . . . . .87

Fig 41. SPI single master multiple slaves configuration. .88

Fig 42. SPI slave transfer format with CPHA = 0. . . . . . .91

Fig 43. SPI slave transfer format with CPHA = 1. . . . . . .92

Fig 44. SPI master transfer format with CPHA = 0.. . . . .93

Fig 45. SPI master transfer format with CPHA = 1.. . . . .94

Fig 46. Comparator input and output connections. . . . . .96

Fig 47. Comparator configurations. (Suppose PGA1 is

disabled, or gain = 1). . . . . . . . . . . . . . . . . . . . . .97

Fig 48. PGA1 block diagram. . . . . . . . . . . . . . . . . . . . . . 98

Fig 49. Watchdog Prescaler.. . . . . . . . . . . . . . . . . . . . .102

Fig 50. Watchdog Timer in Watchdog Mode

(WDTE = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Fig 51. Watchdog Timer in Timer Mode (WDTE = 0).. . 107

Fig 52. Forcing ISP mode. . . . . . . . . . . . . . . . . . . . . . . 118