NXP Semiconductors UM10310 2.8 Clock sources switch on the fly

UM10310_1 © NXP B.V. 2008. All rights reserved.

User manual Rev. 01 — 1 December 2008 24 of 139

NXP Semiconductors UM10310

P89LPC9321 User manual

2.8 Clock sources switch on the fly

P89LPC9321 can implement clock source switch in any sources of watchdog oscillator,

7/14MHz IRC oscillator, external crystal oscillator and external clock input during code is

running. CLKOK bit in register CLKCON is read only and used to indicate the clock switch

status. When CLKOK is ‘0’, clock switch is processing, not completed. When CLKOK is

‘1’, clock switch is completed. When start new clock source switch, CLKOK is cleared

automatically. Notice that when CLKOK is ‘0’, Writing to CLKCON register is not allowed.

During reset, CLKCON register value comes from UCFG1 and UCFG2. The reset value of

CLKCON.2 to CLKCON.0 come from UCFG1.2 to UCFG1.0 and reset value of CLKDBL

bit comes from UCFG2.7.

Note: The oscillator must be configured in one of the following modes: Low frequency crystal, medium frequency crystal, or high

frequency crystal.

(1) A series resistor may be required to limit crystal drive levels. This is especially important for low frequency crystals (see text).

Fig 8. Block diagram of oscillator control.

÷2

002aae108

RTC

CPU

WDT

DIVM CCLK

UART

OSCCLK

I2C-BUS

PCLK

TIMER 0 AND

TIMER 1

HIGH FREQUENCY

MEDIUM FREQUENCY

LOW FREQUENCY

XTAL1

XTAL2

RC OSCILLATOR

WITH CLOCK DOUBLER

WATCHDOG

OSCILLATOR

(7.3728 MHz/14.7456 MHz ± 1 %) PCLK

RCCLK

SPI CCU

32 × PLL

(400 kHz ± 5 %)

Table 7. Clock control register (CLKCON - address FFDEh) bit allocation

Bit 76543210

Symbol CLKOK - - XTALWD CLKDBL FOSC2 FOSC1 FOSC0

Reset1000xxxx

Table 8. Clock control register (CLKCON - address FFDEh) bit description

Bit Symbol Description

2:0 FOSC2, FOSC1,

FOSC0 CPU oscillator type selection for clock switch. See Section 2 for additional

information. Combinations other than those shown in Table9 are reserved for future

use should not be used.

3 CLKDBL Clock doubler option for clock switch. When set, doubles the output frequency of the

internal RC oscillator.

4 XTALWD external crystal oscillator as the clock source of watchdog timer. When =0, disable

external crystal oscillator as the clock source of watchdog timer.

6:5 - reserved

7 CLKOK Clock switch completed flag. When = 1, clock switch is completed. When =0, clock

switch is processing and writing to register CLKCON is not allowed.

Contents

Main Contact information User manual Rev. 01 1 December 2008 3 of 139 NXP Semiconductors UM10310 P89LPC9321 User manual 1. Introduction 1.1 Pin configuration Fig 1. TSSOP28 pin configuration P89LPC9321FDH Fig 2. PLCC28 pin configuration Fig 3. DIP28 pin configuration P89LPC9321FA P89LPC9321FN 1.2 Pin description Page Page User manual Rev. 01 1 December 2008 8 of 139 P89LPC9321 User manual 1.3 Functional diagram P89LPC9321 Fig 4. Functional diagram User manual Rev. 01 1 December 2008 9 of 139 P89LPC9321 User manual 1.4 Block diagram Fig 5. Block diagram P89LPC9321 Page Page Page Page Page Page Page Page Page Page User manual Rev. 01 1 December 2008 20 of 139 1.6 Memory organization Fig 6. P89LPC9321 memory map 2. Clocks 2.1 Enhanced CPU 2.2 Clock definitions 2.2.1 Oscillator Clock (OSCCLK) 2.3 External crystal oscillator option 2.4 Clock output 2.5 On-chip RC oscillator option 2.6 Watchdog oscillator option 2.7 External clock input option 2.8 Clock sources switch on the fly 2.9 Oscillator Clock (OSCCLK) wake-up delay 2.10 CPU Clock (CCLK) modification: DIVM register 2.11 Low power select 3. Interrupts 3.1 Interrupt priority structure 3.2 External Interrupt pin glitch suppression 4. I/O ports 4.1 Port configurations 4.2 Quasi-bidirectional output configuration 4.3 Open drain output configuration NXP Semiconductors UM10310 4.4 Input-only configuration 4.5 Push-pull output configuration 4.6 Port 0 and Analog Comparator functions 4.7 Additional port features 5. Power monitoring functions 5.1 Brownout detection 5.2 Power-on detection 5.3 Power reduction modes 6. Reset 6.1 Reset vector 7. Timers 0 and 1 7.1 Mode 0 7.2 Mode 1 7.3 Mode 2 7.4 Mode 3 7.5 Mode 6 Fig 15. Timer/counter 0 or 1 in Mode 0 (13-bit counter). Fig 16. Timer/counter 0 or 1 in mode 1 (16-bit counter). Fig 17. Timer/counter 0 or 1 in Mode 2 (8-bit auto-reload). 7.6 Timer overflow toggle output 8. Real-time clock system timer Fig 18. Timer/counter 0 Mode 3 (two 8-bit counters). Fig 19. Timer/counter 0 or 1 in mode 6 (PWM auto-reload). 8.1 Real-time clock source 8.2 Changing RTCS1/RTCS0 8.3 Real-time clock interrupt/wake-up 8.3.1 Real-time clock read back 8.4 Reset sources affecting the Real-time clock Page 9. Capture/Compare Unit (CCU) 9.3 Basic timer operation Page 9.4 Output compare 9.5 Input capture 9.6 PWM operation 9.7 Alternating output mode 9.8 Synchronized PWM register update 9.9 HALT 9.10 PLL operation Page Page Page 10. UART 10.1 Mode 0 10.2 Mode 1 10.3 Mode 2 10.4 Mode 3 10.5 SFR space 10.6 Baud Rate generator and selection 10.7 Updating the BRGR1 and BRGR0 SFRs 10.8 Framing error 10.9 Break detect Page 10.10 More about UART Mode 0 10.11 More about UART Mode 1 10.12 More about UART Modes 2 and 3 Fig 29. Serial Port Mode 2 or 3 (only single transmit buffering case is shown) If SM2 = 1 in modes 2 and 3, RI and FE behaves as in the following table. 10.13 Framing error and RI in Modes 2 and 3 with SM2 = 1 Fig 28. Serial Port Mode 1 (only single transmit buffering case is shown) 10.14 Break detect 10.15 Double buffering 10.16 Double buffering in different modes 10.17 Transmit interrupts with double buffering enabled (Modes 1, 2, and 3) 10.18 The 9th bit (bit 8) in double buffering (Modes 1, 2, and 3) 10.19 Multiprocessor communications 10.20 Automatic address recognition 11. I2C interface 11.1 I2C data register 11.2 I2C slave address register 11.3 I2C control register 11.4 I2C Status register 11.5 I2C SCL duty cycle registers I2SCLH and I2SCLL 11.6 I2C operation modes 11.6.1 Master Transmitter mode 11.6.2 Master Receiver mode 11.6.3 Slave Receiver mode 11.6.4 Slave Transmitter mode Fig 37. I2C serial interface block diagram. Page Page Page Page Page 12. Serial Peripheral Interface (SPI) Page Page Fig 39. SPI single master single slave configuration. Fig 40. SPI dual device configuration, where either can be a master or a slave. 12.1 Configuring the SPI 12.2 Additional considerations for a slave 12.3 Additional considerations for a master 12.4 Mode change on SS 12.5 Write collision 12.6 Data mode Fig 42. SPI slave transfer format with CPHA = 0. Fig 43. SPI slave transfer format with CPHA = 1. P89LPC9321 User manual Fig 44. SPI master transfer format with CPHA = 0. 12.7 SPI clock prescaler select 13. Analog comparators 13.1 Comparator configuration Page 13.2 Internal reference voltage 13.3 Comparator input pins 13.4 Comparator interrupt 13.5 Comparators and power reduction modes 13.6 Comparators configuration example 13.7 Programmable Gain Amplifier (PGA) Page 14. Keypad interrupt (KBI) 15. Watchdog timer (WDT) 15.1 Watchdog function 15.2 Feed sequence NXP Semiconductors UM10310 (3) Tabl e 99 shows sample P89LPC9321 timeout values. tclks 2 ()255 1+()1 1048577=+= 15.3 Watchdog clock source 15.4 Watchdog Timer in Timer mode 15.5 Power-down operation 15.6 Periodic wake-up from power-down without an external oscillator 16. Additional features 16.1 Software reset 16.2 Dual Data Pointers 17. Data EEPROM 17.1 Data EEPROM read 17.2 Data EEPROM write 17.3 Hardware reset 17.4 Multiple writes to the DEEDAT register 17.5 Sequences of writes to DEECON and DEEDAT registers 17.6 Data EEPROM Row Fill 17.7 Data EEPROM Block Fill 18. Flash memory 18.1 General description 18.2 Features Page Page Page 18.5 In-circuit programming (ICP) 18.6 ISP and IAP capabilities of the P89LPC9321 18.7 Boot ROM 18.8 Power on reset code execution 18.9 Hardware activation of Boot Loader 18.10 In-system programming (ISP) 18.11 Using the In-system programming (ISP) Page Page 18.12 In-application programming (IAP) 18.13 IAP authorization key 18.14 Flash write enable 18.15 Configuration byte protection 18.16 IAP error status Page Page Page 18.17 User configuration bytes 18.18 User security bytes This device has three security bits associated with each of its eight sectors, as shown in Table116 18.19 Boot Vector register 18.20 Boot status register Page 19. Instruction set Page Page 20. Legal information 20.1 Definitions 20.2 Disclaimers 20.3 Trademarks 21. Tables Page 22. Figures 23. Contents