NXP Semiconductors UM10310

User manual Rev. 01 — 1 December 2008 58 of 139

P89LPC9321 User manual

Table 47. CCU interrupt flag register (TIFR2 - address E9h) bit allocation

Bit 76543210

Symbol TOIF2 TOCF2D TOCF2C TOCF2B TOCF2A - TICF2B TICF2A

Reset00000x00

Table 48. CCU interrupt flag register (TIFR2 - address E9h) bit description

Bit Symbol Description

0 TICF2A Input Capture Channel A Interrupt Flag Bit. Set by hardware when an input capture event is detected.

Cleared by software.

1 TICF2B Input Capture Channel B Interrupt Flag Bit. Set by hardware when an input capture event is detected.

Cleared by software.

2 - Reserved for future use. Should not be set to logic1 by user program.

3 TOCF2A Output Compare Channel A Interrupt Flag Bit. Set by hardware when the contents of TH2:TL2 match that

of OCRHA:OCRLA. Compare channel A must be enabled in order to generate this interrupt. If EA bit in

IEN0, ECCU bit in IEN1 and TOCIE2A bit are all set, the program counter will vectored to the

corresponding interrupt. Cleared by software.

4 TOCF2B Output Compare Channel B Interrupt Flag Bit. Set by hardware when the contents of TH2:TL2 match that

of OCRHB:OCRLB. Compare channel B must be enabled in order to generate this interrupt. If EA bit in

IEN0, ECCU bit in IEN1 and TOCIE2B bit are set, the program counter will vectored to the corresponding

interrupt. Cleared by software.

5 TOCF2C Output Compare Channel C Interrupt Flag Bit. Set by hardware when the contents of TH2:TL2 match that

of OCRHC:OCRLC. Compare channel C must be enabled in order to generate this interrupt. If EA bit in

IEN0, ECCU bit in IEN1 and TOCIE2C bit are all set, the program counter will vectored to the

corresponding interrupt. Cleared by software.

6 TOCF2D Output Compare Channel D Interrupt Flag Bit. Set by hardware when the contents of TH2:TL2 match that

of OCRHD:OCRLD. Compare channel D must be enabled in order to generate this interrupt. If EA bit in

IEN0, ECCU bit in IEN1 and TOCIE2D bit are all set, the program counter will vectored to the

corresponding interrupt. Cleared by software.

7 TOIF2 CCU Timer Overflow Interrupt Flag bit. Set by hardware on CCU Timer overflow. Cleared by software.

Table 49. CCU interrupt control register (TICR2 - address C9h) bit allocation

Bit 76543210

Symbol TOIE2 TOCIE2D TOCIE2C TOCIE2B TOCIE2A - TICIE2B TICIE2A

Reset00000x00

Table 50. CCU interrupt control register (TICR2 - address C9h) bit description

Bit Symbol Description

0 TICIE2A Input Capture Channel A Interrupt Enable Bit. If EA bit and this bit all be set, when a capture event is

detected, the program counter will vectored to the corresponding interrupt.

1 TICIE2B Input Capture Channel B Interrupt Enable Bit. If EA bit and this bit all be set, when a capture event is

detected, the program counter will vectored to the corresponding interrupt.

2 - Reserved for future use. Should not be set to logic1 by user program.

3 TOCIE2A Output Compare Channel A Interrupt Enable Bit. If EA bit and this bit are set to 1, when compare channel

is enabled and the contents of TH2:TL2 match that of OCRHA:OCRLA, the program counter will vectored

to the corresponding interrupt.

4 TOCIE2B Output Compare Channel B Interrupt Enable Bit. If EA bit and this bit are set to 1, when compare channel

B is enabled and the contents of TH2:TL2 match that of OCRHB:OCRLB, the program counter will

vectored to the corresponding interrupt.