SUPER MICRO Computer X7DBi+ user manual Chipset Overview, Xeon Dual Core Processors

Chapter 1: Introduction

1-2 Chipset Overview

Built upon the functionality and the capability of the 5000P chipset, the X7DBi+ motherboard provides the performance and feature set required for dual processor- based servers with configuration options optimized for communications, presenta- tion, storage, computation or database applications. The 5000P chipset supports a single or dual Intel 64-bit Quad core/dual core processor(s) with front side bus speeds of up to 1.333 GHz. The chipset consists of the 5000P Memory Controller Hub (MCH) and the Enterprise South Bridge 2 (ESB2).

The 5000P MCH chipset is designed for symmetric multiprocessing across two independent front side bus interfaces. Each front side bus uses a 64-bit wide, 1.333 GHz data bus that transfers data at 10.7 GB/sec. In addition, the 5000P chipset offers a wide range of RAS features, including memory interface ECC, x4/ x8 Single Device Data Correction, CRC, parity protection, memory mirroring and memory sparing.

The Xeon Dual Core Processors

*L1 Cache Size: Instruction Cache (32KB/16KB), Data Cache (32KB/24KB)

*L2 Cache Size: 4MB (2MB per core)

*Data Bus Transfer Rate: 8.5 GB/s

*Package: FC-LGA6/FC-LGA4, 771 Lands

The Xeon Quad Core Processors

*L1 Cache Size: Instruction Data Cache (32KB per core)

*L2 Cache Size: Shared 4MB per die (8MB Total Cache per processor)

*Data Bus Transfer Rate: 8.5 GB/s

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