6Ć80
Kerneldiagnostics are executed each time the front panel ON/STANDBY
switch is set to ON. The CSA 803C performs powerĆondiagnostics on its
microprocessor subsystemsand SelfĆTest diagnostics on all of its major
circuits.
When Kerneldiagnostics begin, the messages
and are displayed. If the CSA 803C is poweredĆon
from a cold condition, then the diagnostics may complete before the CRT is
warmed up and able to display these messages.
Diagnostic routines are performed in parallel on each of the instrument's
processorsubsystems: Display, Executive, Time Base, and Acquisition.
Followingsuccessful execution of their Kernel diagnostics, the Acquisition
processor attempts to communicate with the Time Base processor and the
TimeBase and Display processors attempt to communicate with the ExecuĆ
tiveprocessor.
The Executiveprocessor will continue SelfĆTest diagnostics even if it is the
only processor that has successfully completed its Kerneldiagnostics.
In the case where the Display processor has not communicated successfully
with the Executive processor,the message indicating that SelfĆTest diagnosĆ
tics are beginning will not appear on the screen. Kerneldiagnostic failures
may be indicated by the message, ,or
on the screen and/or a single highĆlow beep and illuminated
menubuttons.
If either the Display,Time Base, or Acquisition processors do not successfulĆ
ly pass their communications stage, then the CSA 803C automatically enters
Extended Diagnostics at the end of the SelfĆTestdiagnostics. If the Display
processor is at fault, then the Extended Diagnostic menu will not appear on
thescreen.
The Kerneldiagnostic tests execute concurrently in all three subsystem
processor circuitsat powerĆon. Hardware critical to diagnostic operation is
verified, such as ROM, RAM, DMAs, timers, and interrupt control circuitry.
Forthe Executive Processor, this requires checking basic operation for most
boards in the card cage (that is, those boards plugged in to the A13 Mother
board). The last step of Kerneldiagnostics for the Display, Time Base, and
Acquisition processors is to verify communication. Within each processor,all
Kerneldiagnostics must execute without failures before the SelfĆTest diagĆ
nostics canexecute. However, the Executive processor continues with its
SelfĆTestdiagnostics despite a communication failure encountered with the
Display and/or Time Base processors; additionally,the Time Base processor
does not halt when it has a communication failure with the Acquisition
processor.
Since the condition of the instrument is unknown at powerĆon,when a kernel
failure occurs, Kerneldiagnostics in the Executive, Time Base, and AcquisiĆ
tion processors do not attempt to display error index codes. Instead, these
processors generate hexidecimal (hex) numbers that are read as a series of
binary bits, such as XXX1 0101 (hex error code 15) for the Executive
processor,0100 (hex error code 4) for the Time Base processor, or