Block Diagram Descriptions
CSA 803C Service Manual 3Ć21
Time Base/Controller Interface
Data is transferred to and from the TimeBase/Controller subsystem and to
and from the MMU IC through this interface.
Executive Processor (EXP) Interface
This circuitry consists of bidirectional buffers, address mapping programĆ
mable array logic (PAL),and interface timing control PALs. This circuitry
directs data flow to the EXP from the MMU IC and vice versa.
Display IC
Thiscomponent consists of the following functional circuits:
CRTcontroller
Video output circuitry
Compressorcircuit
The basic function of the CRT Controller is to produce VIDEO and SYNC
signals that indicate to the CRT where to position video information. The
controller is virtually automatic in operation and invisible to the firmware
programmer with the exception of several internal registers that must be
initialized at powerĆon.
The video output circuitry is where the hardware recognizes and displays
specific datastructures; the rasterĆscan CRT displays the contents of the bit
map.
During the refresh of the screen, the hardware acquires bit map data along
with waveform display data to yield a final color index.
The compressor circuit receives a waveform composed of several possible
number of data points and outputs 512 pairs (one minimum and one maxiĆ
mum) to the display.
Microprocessor
This component transforms the entire Display subsystem into an intelligent
peripheral dedicated to operating the display.The firmware that controls the
Display subsystem executes from ROM in the microprocessor's address
space. The clock for this microprocessor operates at a frequency of 8 MHz.
Bit Map RAM
This circuit consists of 256 Kbytes of RAM, divided into 4Ćbit planes of
65,536 bytes each. Three of the bit planes are for text and the remaining bit
plane is for XY,variable persistence, and infinite persistence. Each bit in a
plane represents a single pixel of the display.Setting the representative pixel
bit in each of the planes controls the color or intensity.