Theory of Operation
3Ć2 MTG100 & MTG300 MPEG Generator Service Manual
started, the BUFFER LED on the front panel lights, unless the output buffer
empty.
This block updates the PCR and PTS/DTS values, interfaces the peripheral
circuit of the output buffer/clock and the CPU module, and converts parallel
format data to SSI format data. For updating the PCR value, when the PCR
packet is detected, the value of the packet is added to the value of the 27 MHz
counter in the FPGA.
This block outputs the control signals produced by the PLL section, such as
clock, the data signal from the inserter, PSYNC, and DVALID in single-end or
differential 50 W. These signals are converted to TTL, ECL, or LVDS levels.
This block also produces SSI and ASI signals based on DATA signals from
inserter, control signals, and the 27 MHz system reference signal, and outputs
them at 75 W. These output signals can be High Z under control of the CPU.
This block generates four types of clock signals and supplies them to the A10
Main board: 27 MHz clock signal as a system reference, 1–64 MHz clock
signal, [(1–64) * 2] MHz clock signal, and [(1–64) / 8] MHz clock signal. To
generate these four types of clock signals, this block has three operation modes:
Internal Reference mode, External Reference mode and External Clock mode.
When the External Reference or External Clock mode is selected from the menu,
the EXT LED on the front panel lights. The PLL LED also lights when the PLL
is locked.
CPU UnitThe CPU Unit consists of the CPU board, A20 Interface board, LAN board, and
backplane.
The backplane has five PCI bus slots. This board receives power from the A40
MISC (Power Distribution & Interface) board and routes it to each board.
The first and second slots of the Backplane contain the CPU board, which is
based on an Intel Pentium processor and runs Vx Works. The CPU board
controls the user interface, display, each hardware block, and the downloading
and uploading of data through the Ethernet interface. This board also has a flash
disk, a 3.5 inch floppy disk drive, and a IDE hard disk drive as peripheral
devices.
The third slot of the Backplane has the PCI Interface board that consists of the
PCI interface chip and its peripheral circuit, and an FPGA that works as an