Xilinx ML403 specifications Expansion Header

Models: ML403

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ML403 Board Information

R

If additional IIC devices are connected to the bus via the expansion header as shown in Figure 13, insert additional pull-up resistors on the external signals connected at pins 31 and 32. The resistor values are dependent on the voltage.

HDR 1 X 32

 

 

1

 

 

2

 

 

3

 

 

4

 

 

5

NC

 

6

 

 

7

 

 

8

 

 

9

 

 

10

NC

 

11

FPGA_PROM_CPLD_TMS

 

12

FPGA_PROM_CPLD_TCK

 

13

EXPANSION_TDO

 

14

CPLD_TDO

 

15

GPIO_LED_N

 

16

GPIO_SW_N

 

17

GPIO_LED_C

 

18

GPIO_SW_C

 

19

GPIO_LED_W

 

20

GPIO_SW_W

 

21

GPIO_LED_S

 

22

GPIO_SW_S

 

23

GPIO_LED_E

 

24

GPIO_SW_E

 

25

GPIO_LED_0

 

26

GPIO_LED_1

VCC2V5

27

GPIO_LED_2

 

28

GPIO_LED_3

Level

29

NC

Translation

30

NC

MOSFETs

IIC_SCL

31

 

 

 

32

 

 

J3

 

IIC_SDA

 

 

 

External pullups

 

 

connect here

X979_13_012

 

 

Internal pullups

 

 

connect here

Figure 13: Expansion Header

XAPP979 (v1.0) February 26, 2007

www.xilinx.com

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Image 11
Xilinx ML403 specifications Expansion Header