Manuals / Xilinx / Computer Equipment / Switch

Xilinx ML403 specifications Arbitrartion Lost Test Simulation

Models: ML403

1 33

Page 27

Simulation

In the ﬁrst test, which is shown in Figure 30, the OPB IIC registers are read to verify the correct reset values. The interrupt registers are written and read. This occurs from 0 - 10 s. Following this, an arbitration test is run. IIC_AA is initially the bus master, with the write CR_AA 0x0d.

X979_30_022307

Figure 30: Arbitrartion Lost Test Simulation

XAPP979 (v1.0) February 26, 2007

www.xilinx.com

Page 27

Image 27

Xilinx ML403 specifications Arbitrartion Lost Test Simulation

Contents

Included Systems SummaryIntroduction IIC PrimerIntroduction Data Transfer on the IIC Bus Reference System Speciﬁcs Reference System SpeciﬁcsOPB IIC Control Register Bits Name Description ML403 XC4VFX12 Address MapOPB IIC Registers OPB IIC Registers AddressStatus Register SR Status Register Bit Deﬁnitions Contd Microchip 24LC04 Conﬁguring the OPB IIC Core24LC04 Control Byte Allocation ML40x Schematic for IIC ConnectionsML40x Resistors Expansion Header Fpga IIC Pins TotalPhase Aardvark AdapterAardvark Control Center Software Projects Executing the Reference System from EDKProjects interfacing to Aardvark Adapter Running the Applications Running the ApplicationsProject HyperTerminal Parameters Using ChipScope with OPB IIC Invoke XPS. Run Hardware → Generate NetlistRun Start → Programs → ChipScope Pro → ChipScope Inserter Start → Programs → ChipScope Pro → ChipScope Pro Analyzer Making Net Connections in ChipScope InserterSetting Up the Chipscope Trigger Linux Kernel Linux KernelBSP Settings Connected Peripherals Simulation SimulationOPB IIC Simulation Signal Name FunctionalityComplete Simulation Arbitrartion Lost Test Simulation Arbitration Lost Test Code Simulation with iicAA as Master Test code with iicAA as Master X97934012907 Test Code for Simulation with iic20 as Master Revision RevisionHistory References