Xilinx ML403 specifications Configuring the OPB IIC Core, Microchip 24LC04

Reference System Specifics

R

Configuring the OPB IIC Core

Figure 8 shows how to specify the values of IIC generics in EDK. To access the dialog box in the figure, double click on the OPB IIC core in the EDK System Assembly View..

X979_08_012907

Figure 8: Specifying the Values of OPB IIC Generics in EDK

Microchip 24LC04

The Microchip Technology 24LC04B-I/ST with 4-KB EEPROM is provided on the ML403 board to store non-volatile data. The EEPROM write protect is tied off on the board to disable its hardware write protect. The IIC bus is extended to the expansion connector to allow additional devices to be added to the IIC bus.

Figure 9 shows IIC Bus Devices on the ML403.

XC4VSX12

FPGA

SCL

SDA

Microchip 24LC04B

I/O

Expansion

Header

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Figure 9: ML403 IIC Bus

The 24LC04 is organized as two blocks of 256 bytes. It has a page write buffer of up to 16 bytes. The 24LC04 operates as an IIC slave. The 24LC04 accepts a control byte which contains control code, block select, and Read/Write fields shown in Figure 10. The control code

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