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Xilinx ML403 specifications Simulation with iicAA as Master

Models: ML403

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Simulation

The second test, shown in Figure 32, runs from 575 s to 790 .s, Ths master, AA, receives 3C and 55 from 20. The following stimuli / results is seen in the opb_iic.wlf ﬁle.

X979_32_022307

Figure 32: Simulation with iic_AA as Master

XAPP979 (v1.0) February 26, 2007

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Xilinx ML403 specifications Simulation with iicAA as Master

Contents

Included Systems SummaryIntroduction IntroductionIIC Primer Data Transfer on the IIC Bus Reference System Speciﬁcs Reference System SpeciﬁcsOPB IIC Registers ML403 XC4VFX12 Address MapOPB IIC Registers Address OPB IIC Control Register Bits Name DescriptionStatus Register SR Status Register Bit Deﬁnitions Contd Microchip 24LC04 Conﬁguring the OPB IIC Core24LC04 Control Byte Allocation ML40x Schematic for IIC ConnectionsML40x Resistors Expansion Header Fpga IIC Pins TotalPhase Aardvark AdapterAardvark Control Center Software Projects Executing the Reference System from EDKProjects interfacing to Aardvark Adapter Project Running the ApplicationsRunning the Applications HyperTerminal Parameters Run Start → Programs → ChipScope Pro → ChipScope Inserter Using ChipScope with OPB IICInvoke XPS. Run Hardware → Generate Netlist Start → Programs → ChipScope Pro → ChipScope Pro Analyzer Making Net Connections in ChipScope InserterSetting Up the Chipscope Trigger Linux Kernel Linux KernelBSP Settings Connected Peripherals Simulation SimulationOPB IIC Simulation Signal Name FunctionalityComplete Simulation Arbitrartion Lost Test Simulation Arbitration Lost Test Code Simulation with iicAA as Master Test code with iicAA as Master X97934012907 Test Code for Simulation with iic20 as Master History RevisionReferences Revision