Texas Instruments TMS320C6452 DSP manual Clock Control, Memory Map, Signal Descriptions

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Peripheral Architecture

2Peripheral Architecture

The DDR2 memory controller can gluelessly interface to most standard DDR2 SDRAM devices and supports such features as self-refresh mode and prioritized refresh. In addition, it provides flexibility through programmable parameters such as the refresh rate, CAS latency, and many SDRAM timing parameters.

The following sections describe the architecture of the DDR2 memory controller as well as how to interface and configure it to perform read and write operations to DDR2 SDRAM devices. Also, Section 3 provides a detailed example of interfacing the DDR2 memory controller to a common DDR2 SDRAM device.

2.1Clock Control

The DDR2 memory controller is clocked directly from the output of the second phase-locked loop (PLL2) of the device. The PLL2 multiplies its input clock by 20. This clock is divided by 2 to generate DDR_CLK. The frequency of DDR_CLK can be determined by using the following formula:

DDR_CLK frequency = (PLL2 input clock frequency×20)/2 = PLL2 input clock frequency×10

The second output clock of the DDR2 memory controller, DDR_CLK, is the inverse of DDR_CLK. For more information on the PLL2, see the device-specific data manual.

2.2Memory Map

Please see the device-specific data manual for information describing the device memory map.

2.3Signal Descriptions

The DDR2 memory controller signals are shown in Figure 2 and described in Table 1. The following features are included:

∙The maximum width for the data bus (DDR_D[31:0]) is 32-bits.

∙The address bus (DDR_A[13:0]) is 14-bits wide with an additional 3 bank address pins (DDR_BA[2:0]).

∙Two differential output clocks (DDR_CLK and DDR_CLK) driven by internal clock sources.

∙Command signals: Row and column address strobe (DDR_RAS and DDR_CAS), write enable strobe (DDR_WE), data strobe (DDR_DQS[3:0] and DDR_DQS[3:0]), and data mask (DDR_DQM[3:0]).

∙One chip select signal (DDR_CS) and one clock enable signal (DDR_CKE).

∙Two on-die termination output signals (DDR_ODT[1:0]).

SPRUF85 –October 2007

DSP DDR2 Memory Controller

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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Reference Guides Data ManualRelated Documents From Texas Instruments Related Documents From Texas Instruments Purpose of the Peripheral FeaturesFunctional Block Diagram Industry Standards Compliance Statement Memory Map Signal DescriptionsClock Control Pin Description DDR2 Memory Controller Signal DescriptionsProtocol Descriptions DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Command FunctionCOL Mode Register Set MRS and EmrsRefresh Mode Ddrclk MRS/EMRS Ddrcke Ddrcs Ddrras Ddrcas DdrweDdrcs Ddrras Ddrcas Ddrwe Activation ActvDeactivation Dcab and Deac Dcab CommandDDR2 Read Command Read CommandMemory Width Maximum Addressable Bytes Write WRT CommandMemory Width and Byte Alignment Addressable Memory RangesIbank Bank Configuration Register Fields for Address MappingAddress Mapping Bit Field Bit Value Bit DescriptionLogical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Fifo Description DDR2 Memory Controller InterfaceCommand Ordering and Scheduling, Advanced Concept DDR2 Memory Controller Fifo Block DiagramCommand Starvation Urgency Level Description Refresh SchedulingPossible Race Condition Refresh Urgency LevelsReset Sources Self-Refresh ModeReset Considerations 11 DDR2 Sdram Memory Initialization 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Mode Register Configuration DDR2 Sdram Extended Mode Register 1 ConfigurationEdma Event Support 11.2 DDR2 Sdram Initialization After Reset11.3 DDR2 Sdram Initialization After Register Configuration Interrupt SupportConnecting the DDR2 Memory Controller to DDR2 Sdram Using the DDR2 Memory ControllerConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Function Selection Programming the Sdram Configuration Register SdcfgSdcfg Configuration Programming the Sdram Refresh Control Register SdrfcSDTIM1 Configuration DDR2 Memory Refresh SpecificationSdrfc Configuration Configuring Sdram Timing Registers SDTIM1 and SDTIM2Name Description SDTIM2 ConfigurationDmcctl Configuration DDR2 Sdram Data Register Field Sheet ParameterOffset Acronym Register Description DDR2 Memory Controller RegistersBit Field Value Description Module ID and Revision Register MidrDDR2 Memory Controller Status Register Dmcstat Module ID and Revision Register Midr Field DescriptionsSdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register SdcfgSdram Configuration Register Sdcfg Field Descriptions Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Refresh Control Register SdrfcTras TRC Trrd Sdram Timing 1 Register SDTIM1Sdram Timing 1 Register SDTIM1 Field Descriptions Trfc TRP Trcd TWRDDR2 memory data sheet. Calculate using this formula Tsxrd Trtp Tcke Sdram Timing 2 Register SDTIM2Sdram Timing 2 Register SDTIM2 Field Descriptions Todt TsxnrPrioraise Burst Priority Register BprioBurst Priority Register Bprio Field Descriptions Rese DDR2 Memory Controller Control Register DmcctlRfid Products ApplicationsDSP