Texas Instruments TMS320C6452 DSP Sdram Timing 2 Register SDTIM2, Todt Tsxnr, Tsxrd Trtp Tcke

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DDR2 Memory Controller Registers

4.6SDRAM Timing 2 Register (SDTIM2)

Like the SDRAM timing 1 register (SDTIM1), the SDRAM timing 2 register (SDTIM2) also configures the DDR2 memory controller to meet the AC timing specification of the DDR2 memory. See the DDR2 memory data sheet for information on the appropriate values to program each field. The bit fields in the SDTIM2 register are only writeable when the TIMUNLOCK bit of the SDRAM Configuration register (SDCFG) is unlocked. SDTIM2 is shown in Figure 25 and described in Table 23.

Figure 25. SDRAM Timing 2 Register (SDTIM2)

31

25

24

23

22

 

16

Reserved

 

T_ODT

 

 

T_SXNR

R-0x0

 

R/W-0x3

 

 

R/W-0x7F

15

 

8

7

5

4

0

T_SXRD

 

 

 

T_RTP

 

T_CKE

R/W-0xFF

 

 

 

R/W-0x7

 

R/W-0x1F

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset; -x = value is indeterminate after reset;

Table 23. SDRAM Timing 2 Register (SDTIM2) Field Descriptions

Bit

Field

Value

Description

31-25

Reserved

 

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

24-23

T_ODT

 

These bits specify the number of DDR_CLK cycles from ODT enable to write data driven for DDR2

 

 

 

SDRAM. T_ODT must be less than the CAS latency minus one. Calculate using this formula:

 

 

 

T_ODT = CAS latency - taond - 1

22-16

T_SXNR

0-7Fh

These bits specify the minimum number of DDR_CLK cycles from a self_refresh exit to any other

 

 

 

command except a read command, minus 1. The value for these bits can be derived from the tSXNR

 

 

 

AC timing parameter in the DDR2 data sheet. Calculate using this formula:

 

 

 

T_SXNR = (tSXNR/DDR_CLK) - 1

15-8

T_SXRD

0-FFh

These bits specify the minimum number of DDR_CLK cycles from a self_refresh exit to a read

 

 

 

command, minus 1. The value for these bits can be derived from the tSXRD AC timing parameter in

 

 

 

the DDR2 data sheet. Calculate using this formula:

 

 

 

T_SXRD = tSXRD - 1

7-5

T_RTP

0-7h

These bits specify the minimum number of DDR_CLK cycles from a last read command to a

 

 

 

precharge command, minus 1. The value for these bits can be derived from the trtp AC timing

 

 

 

parameter in the DDR2 data sheet. Calculate using this formula:

 

 

 

T_RTP = (trtp/DDR_CLK) - 1

4-0

T_CKE

0-1Fh

These bits specify the minimum number of DDR_CLK cycles between transitions on the DDR_CKE

 

 

 

pin, minus 1. The value for these bits can be derived from the tcke AC timing parameter in the

 

 

 

DDR2 data sheet. Calculate using this formula:

T_CKE = tcke - 1

SPRUF85 –October 2007

DSP DDR2 Memory Controller

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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Reference Guides Data ManualRelated Documents From Texas Instruments Related Documents From Texas Instruments Functional Block Diagram FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Clock Control Signal DescriptionsMemory Map Pin Description DDR2 Memory Controller Signal DescriptionsProtocol Descriptions DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Command FunctionCOL Mode Register Set MRS and EmrsRefresh Mode Ddrclk MRS/EMRS Ddrcke Ddrcs Ddrras Ddrcas DdrweDdrcs Ddrras Ddrcas Ddrwe Activation ActvDeactivation Dcab and Deac Dcab CommandDDR2 Read Command Read CommandMemory Width Maximum Addressable Bytes Write WRT CommandMemory Width and Byte Alignment Addressable Memory RangesIbank Bank Configuration Register Fields for Address MappingAddress Mapping Bit Field Bit Value Bit DescriptionLogical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Fifo Description DDR2 Memory Controller InterfaceCommand Ordering and Scheduling, Advanced Concept DDR2 Memory Controller Fifo Block DiagramCommand Starvation Urgency Level Description Refresh SchedulingPossible Race Condition Refresh Urgency LevelsReset Considerations Self-Refresh ModeReset Sources 11 DDR2 Sdram Memory Initialization 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Mode Register Configuration DDR2 Sdram Extended Mode Register 1 ConfigurationEdma Event Support 11.2 DDR2 Sdram Initialization After Reset11.3 DDR2 Sdram Initialization After Register Configuration Interrupt SupportConnecting the DDR2 Memory Controller to DDR2 Sdram Using the DDR2 Memory ControllerConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Function Selection Programming the Sdram Configuration Register SdcfgSdcfg Configuration Programming the Sdram Refresh Control Register SdrfcSDTIM1 Configuration DDR2 Memory Refresh SpecificationSdrfc Configuration Configuring Sdram Timing Registers SDTIM1 and SDTIM2Name Description SDTIM2 ConfigurationDmcctl Configuration DDR2 Sdram Data Register Field Sheet ParameterOffset Acronym Register Description DDR2 Memory Controller RegistersBit Field Value Description Module ID and Revision Register MidrDDR2 Memory Controller Status Register Dmcstat Module ID and Revision Register Midr Field DescriptionsSdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register SdcfgSdram Configuration Register Sdcfg Field Descriptions Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Refresh Control Register SdrfcTras TRC Trrd Sdram Timing 1 Register SDTIM1Sdram Timing 1 Register SDTIM1 Field Descriptions Trfc TRP Trcd TWRDDR2 memory data sheet. Calculate using this formula Tsxrd Trtp Tcke Sdram Timing 2 Register SDTIM2Sdram Timing 2 Register SDTIM2 Field Descriptions Todt TsxnrBurst Priority Register Bprio Field Descriptions Burst Priority Register BprioPrioraise Rese DDR2 Memory Controller Control Register DmcctlDSP Products ApplicationsRfid
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