Texas Instruments TMS320C6452 DSP manual Self-Refresh Mode, Reset Considerations, Reset Sources

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Peripheral Architecture

2.9Self-Refresh Mode

Setting the self refresh (SR) bit in the SDRAM refresh control register (SDRFC) to 1 forces the DDR2 memory controller to place the external DDR2 SDRAM in a low-power mode (self refresh), in which the DDR2 SDRAM maintains valid data while consuming a minimal amount of power. When the SR bit is asserted, the DDR2 memory controller continues normal operation until all outstanding memory access requests have been serviced and the refresh backlog has been cleared. At this point, all open pages of DDR2 SDRAM are closed and a self-refresh (SLFRFR) command (an autorefresh command with DDR_CKE low) is issued.

The DDR2 memory controller exits the self-refresh state when a memory access is received or when the SR bit in SDRFC is cleared. While in the self-refresh state, if a request for a memory access is received, the DDR2 memory controller services the memory access request, returning to the self-refresh state upon completion.

The DDR2 memory controller will not exit the self-refresh state (whether from a memory access request or from clearing the SR bit) until T_CKE + 1 cycles have expired since the self-refresh command was issued. The value of T_CKE is defined in the SDRAM timing 2 register (SDTIM2).

After exiting from the self-refresh state, the DDR2 memory controller will not immediately start using commands. Instead, it will wait T_SXNR + 1 clock cycles before issuing non-read commands and T_SXRD + 1 clock cycles before issuing read commands. The SDRAM timing 2 register (SDTIM2) programs the values of T_SXNR and T_SXRD.

2.10Reset Considerations

The DDR2 memory controller has two reset signals, VRST and VCTL_RST. VRST is a module-level reset that resets both the state machine and the DDR2 memory controller memory-mapped registers. VCTL_RST resets the state machine only. If the DDR2 memory controller is reset independently of other peripherals, your software should not perform memory or register accesses while VRST or VCTL_RST are asserted. If memory or register accesses are performed while the DDR2 memory controller is in the reset state, other masters may hang. Following the rising edge of VRST or VCTL_RST, the DDR2 memory controller FIFOs are lost. Table 8 describes the different methods for asserting each reset signal. The Power and Sleep Controller (PSC) acts as a master controller for power management for all of the peripherals on the device.

 

Table 8. Reset Sources

Reset Signal

Reset Source

VRST

Hardware/device reset

VCTL_RST

Power and sleep controller

Figure 16. DDR2 Memory Controller Reset Block Diagram

Hard

reset￿from

PLLCTL1

DDR

PSC

VRST

VCTL_RST

DDR2

memory

controller registers

State

machine

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DSP DDR2 Memory Controller

SPRUF85 –October 2007

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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Data Manual Reference GuidesRelated Documents From Texas Instruments Related Documents From Texas Instruments Purpose of the Peripheral FeaturesFunctional Block Diagram Industry Standards Compliance Statement Memory Map Signal DescriptionsClock Control DDR2 Memory Controller Signal Descriptions Pin DescriptionCommand Function DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Protocol DescriptionsDdrclk MRS/EMRS Ddrcke Ddrcs Ddrras Ddrcas Ddrwe Mode Register Set MRS and EmrsRefresh Mode COLActivation Actv Ddrcs Ddrras Ddrcas DdrweDcab Command Deactivation Dcab and DeacRead Command DDR2 Read CommandAddressable Memory Ranges Write WRT CommandMemory Width and Byte Alignment Memory Width Maximum Addressable BytesBit Field Bit Value Bit Description Bank Configuration Register Fields for Address MappingAddress Mapping IbankLogical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Interface DDR2 Memory Controller Fifo DescriptionDDR2 Memory Controller Fifo Block Diagram Command Ordering and Scheduling, Advanced ConceptCommand Starvation Refresh Urgency Levels Refresh SchedulingPossible Race Condition Urgency Level DescriptionReset Sources Self-Refresh ModeReset Considerations DDR2 Sdram Extended Mode Register 1 Configuration 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Mode Register Configuration 11 DDR2 Sdram Memory InitializationInterrupt Support 11.2 DDR2 Sdram Initialization After Reset11.3 DDR2 Sdram Initialization After Register Configuration Edma Event SupportUsing the DDR2 Memory Controller Connecting the DDR2 Memory Controller to DDR2 SdramConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Programming the Sdram Refresh Control Register Sdrfc Programming the Sdram Configuration Register SdcfgSdcfg Configuration Function SelectionConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 DDR2 Memory Refresh SpecificationSdrfc Configuration SDTIM1 ConfigurationDDR2 Sdram Data Register Field Sheet Parameter SDTIM2 ConfigurationDmcctl Configuration Name DescriptionDDR2 Memory Controller Registers Offset Acronym Register DescriptionModule ID and Revision Register Midr Field Descriptions Module ID and Revision Register MidrDDR2 Memory Controller Status Register Dmcstat Bit Field Value DescriptionSdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field DescriptionsSdram Configuration Register Sdcfg Field Descriptions Sdram Refresh Control Register Sdrfc Sdram Refresh Control Register Sdrfc Field DescriptionsTrfc TRP Trcd TWR Sdram Timing 1 Register SDTIM1Sdram Timing 1 Register SDTIM1 Field Descriptions Tras TRC TrrdDDR2 memory data sheet. Calculate using this formula Todt Tsxnr Sdram Timing 2 Register SDTIM2Sdram Timing 2 Register SDTIM2 Field Descriptions Tsxrd Trtp TckePrioraise Burst Priority Register BprioBurst Priority Register Bprio Field Descriptions DDR2 Memory Controller Control Register Dmcctl ReseRfid Products ApplicationsDSP
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