Texas Instruments TMS320C6452 DSP Address Mapping, Bit Field Bit Value Bit Description, Ibank

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Peripheral Architecture

Figure 10 shows the byte lanes used on the DDR2 memory controller. The external memory is always right aligned on the data bus.

Figure 10. Byte Alignment

 

DDR2 memory controller data bus

 

DDR_D[31:24]

DDR_D[23:16]

DDR_D[15:8]

DDR_D[7:0]

(Byte Lane 3)

(Byte Lane 2)

(Byte Lane 1)

(Byte Lane 0)

 

 

 

 

32-bit memory device

16-bit memory device

2.6Address Mapping

The DDR2 memory controller views external DDR2 SDRAM as one continuous block of memory. This statement is true regardless of the number of memory devices located on the chip select space. The DDR2 memory controller receives DDR2 memory access requests along with a 32-bit logical address from the rest of the system. In turn, DDR2 memory controller uses the logical address to generate a row/page, column, and bank address for the DDR2 SDRAM. The number of column and bank address bits used is determined by the IBANK and PAGESIZE fields (see Table 5). The DDR2 memory controller uses up to 14 bits for the row/page address.

Table 5. Bank Configuration Register Fields for Address Mapping

Bit Field

Bit Value

Bit Description

IBANK

 

Defines the number of internal banks on the external DDR2 memory.

 

0

1 bank

 

1h

2 banks

 

2h

4 banks

 

3h

8 banks

PAGESIZE

 

Defines the page size of each page of the external DDR2 memory.

 

0

256 words (requires 8 column address bits)

 

1h

512 words (requires 9 column address bits)

 

2h

1024 words (requires 10 column address bits)

 

3h

2048 words (requires 11 column address bits)

Figure 11 and Figure 12 show how the logical address bits map to the row, column, and bank bits all combinations of IBANK and PAGESIZE values. Note that the upper four bits of the logical address cannot be used for memory addressing, as the DDR2 memory controller has a maximum addressable memory range of 256 Mbytes.

The DDR2 memory controller address pins provide the row and column address to the DDR2 SDRAM, thus the DDR2 memory controller appropriately shifts the logical address during row and column address selection. The bank address is driven to the DDR2 SDRAM using the bank address pins. The two lower bits of the logical address decode the value of the byte enable pins (only used for accesses less than the width of the DDR2 memory controller data bus).

Figure 11. Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAM

SPRUF85 –October 2007

DSP DDR2 Memory Controller

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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Reference Guides Data ManualRelated Documents From Texas Instruments Related Documents From Texas Instruments Functional Block Diagram FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Clock Control Signal DescriptionsMemory Map Pin Description DDR2 Memory Controller Signal DescriptionsProtocol Descriptions DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Command FunctionCOL Mode Register Set MRS and EmrsRefresh Mode Ddrclk MRS/EMRS Ddrcke Ddrcs Ddrras Ddrcas DdrweDdrcs Ddrras Ddrcas Ddrwe Activation ActvDeactivation Dcab and Deac Dcab CommandDDR2 Read Command Read CommandMemory Width Maximum Addressable Bytes Write WRT CommandMemory Width and Byte Alignment Addressable Memory RangesIbank Bank Configuration Register Fields for Address MappingAddress Mapping Bit Field Bit Value Bit DescriptionLogical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Fifo Description DDR2 Memory Controller InterfaceCommand Ordering and Scheduling, Advanced Concept DDR2 Memory Controller Fifo Block DiagramCommand Starvation Urgency Level Description Refresh SchedulingPossible Race Condition Refresh Urgency LevelsReset Considerations Self-Refresh ModeReset Sources 11 DDR2 Sdram Memory Initialization 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Mode Register Configuration DDR2 Sdram Extended Mode Register 1 ConfigurationEdma Event Support 11.2 DDR2 Sdram Initialization After Reset11.3 DDR2 Sdram Initialization After Register Configuration Interrupt SupportConnecting the DDR2 Memory Controller to DDR2 Sdram Using the DDR2 Memory ControllerConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Function Selection Programming the Sdram Configuration Register SdcfgSdcfg Configuration Programming the Sdram Refresh Control Register SdrfcSDTIM1 Configuration DDR2 Memory Refresh SpecificationSdrfc Configuration Configuring Sdram Timing Registers SDTIM1 and SDTIM2Name Description SDTIM2 ConfigurationDmcctl Configuration DDR2 Sdram Data Register Field Sheet ParameterOffset Acronym Register Description DDR2 Memory Controller RegistersBit Field Value Description Module ID and Revision Register MidrDDR2 Memory Controller Status Register Dmcstat Module ID and Revision Register Midr Field DescriptionsSdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register SdcfgSdram Configuration Register Sdcfg Field Descriptions Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Refresh Control Register SdrfcTras TRC Trrd Sdram Timing 1 Register SDTIM1Sdram Timing 1 Register SDTIM1 Field Descriptions Trfc TRP Trcd TWRDDR2 memory data sheet. Calculate using this formula Tsxrd Trtp Tcke Sdram Timing 2 Register SDTIM2Sdram Timing 2 Register SDTIM2 Field Descriptions Todt TsxnrBurst Priority Register Bprio Field Descriptions Burst Priority Register BprioPrioraise Rese DDR2 Memory Controller Control Register DmcctlDSP Products ApplicationsRfid
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