Texas Instruments TMS320C6452 DSP manual Data Manual, Reference Guides

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Preface

SPRUF85 – October 2007

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About This Manual

This document describes the operation of the DDR2 Memory Controller in the TMS320C6452.

Notational Conventions

This document uses the following conventions.

∙Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h.

∙Registers in this document are shown in figures and described in tables.

–Each register figure shows a rectangle divided into fields that represent the fields of the register. Each field is labeled with its bit name, its beginning and ending bit numbers above, and its read/write properties below. A legend explains the notation used for the properties.

–Reserved bits in a register figure designate a bit that is used for future device expansion.

Note: Acronyms 3PSW, CPSW, CPSW_3G, and 3pGSw are interchangeable and all refer to the 3 port gigabit switch.

Related Documents From Texas Instruments

The following documents describe the TMS320C6452 Digital Signal Processor (DSP). Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box provided at www.ti.com.

Data Manual—

SPRS371 — TMS320C6452 Digital Signal Processor Data Manual describes the signals, specifications and electrical characteristics of the device.

CPU—

SPRU732 — TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide describes the CPU architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digital signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generation comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement of the C64x DSP with added functionality and an expanded instruction set.

Reference Guides—

SPRUF85 — TMS320C6452 DSP DDR2 Memory Controller User's Guide describes the DDR2 memory controller in the TMS320C6452 Digital Signal Processor (DSP). The DDR2/mDDR memory controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAM devices and standard Mobile DDR SDRAM devices.

SPRUF86 — TMS320C6452 Peripheral Component Interconnect (PCI) User's Guide describes the peripheral component interconnect (PCI) port in the TMS320C6452 Digital Signal Processor (DSP). The PCI port supports connection of the C642x DSP to a PCI host via the integrated PCI master/slave bus interface. The PCI port interfaces to the DSP via the enhanced DMA (EDMA) controller. This architecture allows for both PCI master and slave transactions, while keeping the EDMA channel resources available for other applications.

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Preface

SPRUF85 –October 2007

 

 

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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Data Manual Reference GuidesRelated Documents From Texas Instruments Related Documents From Texas Instruments Features Functional Block DiagramPurpose of the Peripheral Industry Standards Compliance Statement Signal Descriptions Clock ControlMemory Map DDR2 Memory Controller Signal Descriptions Pin DescriptionCommand Function DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Protocol DescriptionsDdrclk MRS/EMRS Ddrcke Ddrcs Ddrras Ddrcas Ddrwe Mode Register Set MRS and EmrsRefresh Mode COLActivation Actv Ddrcs Ddrras Ddrcas DdrweDcab Command Deactivation Dcab and DeacRead Command DDR2 Read CommandAddressable Memory Ranges Write WRT CommandMemory Width and Byte Alignment Memory Width Maximum Addressable BytesBit Field Bit Value Bit Description Bank Configuration Register Fields for Address MappingAddress Mapping IbankLogical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Interface DDR2 Memory Controller Fifo DescriptionDDR2 Memory Controller Fifo Block Diagram Command Ordering and Scheduling, Advanced ConceptCommand Starvation Refresh Urgency Levels Refresh SchedulingPossible Race Condition Urgency Level DescriptionSelf-Refresh Mode Reset ConsiderationsReset Sources DDR2 Sdram Extended Mode Register 1 Configuration 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Mode Register Configuration 11 DDR2 Sdram Memory InitializationInterrupt Support 11.2 DDR2 Sdram Initialization After Reset11.3 DDR2 Sdram Initialization After Register Configuration Edma Event SupportUsing the DDR2 Memory Controller Connecting the DDR2 Memory Controller to DDR2 SdramConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Programming the Sdram Refresh Control Register Sdrfc Programming the Sdram Configuration Register SdcfgSdcfg Configuration Function SelectionConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 DDR2 Memory Refresh SpecificationSdrfc Configuration SDTIM1 ConfigurationDDR2 Sdram Data Register Field Sheet Parameter SDTIM2 ConfigurationDmcctl Configuration Name DescriptionDDR2 Memory Controller Registers Offset Acronym Register DescriptionModule ID and Revision Register Midr Field Descriptions Module ID and Revision Register MidrDDR2 Memory Controller Status Register Dmcstat Bit Field Value DescriptionSdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field DescriptionsSdram Configuration Register Sdcfg Field Descriptions Sdram Refresh Control Register Sdrfc Sdram Refresh Control Register Sdrfc Field DescriptionsTrfc TRP Trcd TWR Sdram Timing 1 Register SDTIM1Sdram Timing 1 Register SDTIM1 Field Descriptions Tras TRC TrrdDDR2 memory data sheet. Calculate using this formula Todt Tsxnr Sdram Timing 2 Register SDTIM2Sdram Timing 2 Register SDTIM2 Field Descriptions Tsxrd Trtp TckeBurst Priority Register Bprio Burst Priority Register Bprio Field DescriptionsPrioraise DDR2 Memory Controller Control Register Dmcctl ReseProducts Applications DSPRfid
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