Texas Instruments TMS320C6452 DSP manual Related Documents From Texas Instruments

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Related Documents From Texas Instruments

SPRUF87 — TMS320C6452 DSP Host Port Interface (UHPI) User's Guide describes the host port interface (HPI) in the TMS320C6452 Digital Signal Processor (DSP). The HPI is a parallel port through which a host processor can directly access the CPU memory space. The host device functions as a master to the interface, which increases ease of access. The host and CPU can exchange information via internal or external memory. The host also has direct access to memory-mapped peripherals. Connectivity to the CPU memory space is provided through the enhanced direct memory access (EDMA) controller.

SPRUF89 — TMS320C6452 DSP VLYNQ Port User's Guide describes the VLYNQ port in the TMS320C6452 Digital Signal Processor (DSP). The VLYNQ port is a high-speedpoint-to-point serial interface for connecting to host processors and other VLYNQ compatible devices. It is a full-duplex serial bus where transmit and receive operations occur separately and simultaneously without interference.

SPRUF90 — TMS320C6452 DSP 64-Bit Timer User's Guide describes the operation of the 64-bit timer in the TMS320C6452 Digital Signal Processor (DSP). The timer can be configured as a general-purpose 64-bit timer, dual general-purpose 32-bit timers, or a watchdog timer.

SPRUF91 — TTMS320C6452 DSP Multichannel Audio Serial Port (McASP) User's Guide describes the multichannel audio serial port (McASP) in the TMS320C6452 Digital Signal Processor (DSP). The McASP functions as a general-purpose audio serial port optimized for the needs of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM) stream, Inter-Integrated Sound (I2S) protocols, and intercomponent digital audio interface transmission (DIT).

SPRUF92 — TMS320C6452 DSP Serial Port Interface (SPI) User's Guide discusses the Serial Port Interface (SPI) in the TMS320C6452 Digital Signal Processor (DSP). This reference guide provides the specifications for a 16-bit configurable, synchronous serial peripheral interface. The SPI is a programmable-length shift register, used for high speed communication between external peripherals or other DSPs.

SPRUF93 — TMS320C6452 DSP Universal Asynchronous Receiver/Transmitter (UART) User's Guide describes the universal asynchronous receiver/transmitter (UART) peripheral in the TMS320C6452 Digital Signal Processor (DSP). The UART peripheral performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data received from the CPU.

SPRUF94 — TMS320C6452 DSP Inter-Integrated Circuit (I2C) Module User's Guide describes the inter-integrated circuit (I2C) peripheral in the TMS320C6452 Digital Signal Processor (DSP). The I2C peripheral provides an interface between the DSP and other devices compliant with the I2C-bus specification and connected by way of an I2C-bus. External components attached to this 2-wire serial bus can transmit and receive up to 8-bit wide data to and from the DSP through the I2C peripheral. This document assumes the reader is familiar with the I2C-bus specification.

SPRUF95 — TMS320C6452 DSP General-Purpose Input/Output (GPIO) User's Guide describes the general-purpose input/output (GPIO) peripheral in the TMS320C6452 Digital Signal Processor (DSP). The GPIO peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs. When configured as an input, you can detect the state of the input by reading the state of an internal register. When configured as an output, you can write to an internal register to control the state driven on the output pin.

SPRUF96 — TMS320C6452 DSP Telecom Serial Interface Port (TSIP) User'sGuide is a multi-link serial interface consisting of a maximum of two transmit data signals (or links), two receive data signals (or links), two frame sync input signals, and two serial clock inputs. Internally the TSIP offers single channel of timeslot data management and single DMA capability that allow individual timeslots to be selectively processed.

SPRUF85 –October 2007

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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Reference Guides Data ManualRelated Documents From Texas Instruments Related Documents From Texas Instruments Functional Block Diagram FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Clock Control Signal DescriptionsMemory Map Pin Description DDR2 Memory Controller Signal DescriptionsProtocol Descriptions DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Command FunctionCOL Mode Register Set MRS and EmrsRefresh Mode Ddrclk MRS/EMRS Ddrcke Ddrcs Ddrras Ddrcas DdrweDdrcs Ddrras Ddrcas Ddrwe Activation ActvDeactivation Dcab and Deac Dcab CommandDDR2 Read Command Read CommandMemory Width Maximum Addressable Bytes Write WRT CommandMemory Width and Byte Alignment Addressable Memory RangesIbank Bank Configuration Register Fields for Address MappingAddress Mapping Bit Field Bit Value Bit DescriptionLogical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Fifo Description DDR2 Memory Controller InterfaceCommand Ordering and Scheduling, Advanced Concept DDR2 Memory Controller Fifo Block DiagramCommand Starvation Urgency Level Description Refresh SchedulingPossible Race Condition Refresh Urgency LevelsReset Considerations Self-Refresh ModeReset Sources 11 DDR2 Sdram Memory Initialization 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Mode Register Configuration DDR2 Sdram Extended Mode Register 1 ConfigurationEdma Event Support 11.2 DDR2 Sdram Initialization After Reset11.3 DDR2 Sdram Initialization After Register Configuration Interrupt SupportConnecting the DDR2 Memory Controller to DDR2 Sdram Using the DDR2 Memory ControllerConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Function Selection Programming the Sdram Configuration Register SdcfgSdcfg Configuration Programming the Sdram Refresh Control Register SdrfcSDTIM1 Configuration DDR2 Memory Refresh SpecificationSdrfc Configuration Configuring Sdram Timing Registers SDTIM1 and SDTIM2Name Description SDTIM2 ConfigurationDmcctl Configuration DDR2 Sdram Data Register Field Sheet ParameterOffset Acronym Register Description DDR2 Memory Controller RegistersBit Field Value Description Module ID and Revision Register MidrDDR2 Memory Controller Status Register Dmcstat Module ID and Revision Register Midr Field DescriptionsSdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register SdcfgSdram Configuration Register Sdcfg Field Descriptions Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Refresh Control Register SdrfcTras TRC Trrd Sdram Timing 1 Register SDTIM1Sdram Timing 1 Register SDTIM1 Field Descriptions Trfc TRP Trcd TWRDDR2 memory data sheet. Calculate using this formula Tsxrd Trtp Tcke Sdram Timing 2 Register SDTIM2Sdram Timing 2 Register SDTIM2 Field Descriptions Todt TsxnrBurst Priority Register Bprio Field Descriptions Burst Priority Register BprioPrioraise Rese DDR2 Memory Controller Control Register DmcctlDSP Products ApplicationsRfid
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