Texas Instruments TMS320C6452 DSP Interrupt Support, Edma Event Support, Emulation Considerations

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Peripheral Architecture

Table 10. DDR2 SDRAM Extended Mode Register 1 Configuration (continued)

Mode

Mode Register

 

 

Register Bit

Field

Init Value

Description

2

ODT Value (Rtt)

1

On-die termination effective resistance (Rtt) bits. Together

 

 

 

with bit 2, this bit selects the value for Rtt as 75Ω.

1

Output Driver

SDCFG.DDR_DRIVE

Output driver impedance control bits. Initialized using the

 

Impedance

 

DDR_DRIVE bit of the SDRAM configuration register

 

 

 

(SDCFG).

0

DLL Enable

0

DLL enable/disable bits. DLL is always enabled.

2.11.2DDR2 SDRAM Initialization After Reset

After a hard or a soft reset, the DDR2 memory controller will automatically start the initialization sequence. The DDR2 memory controller will use the default values in the SDRAM timing 1 and timing 2 registers and the SDRAM configuration register to configure the mode registers of the DDR2 SDRAM device(s). Note that since a soft reset does not reset the DDR2 memory controller registers, an initialization sequence started by a soft reset would use the register values from a previous configuration.

2.11.3DDR2 SDRAM Initialization After Register Configuration

The initialization sequence can also be initiated by performing a write to the two least-significant bytes in the SDRAM configuration register (SDCFG). Using this approach, data and commands stored in the DDR2 memory controller FIFOs are not lost and the DDR2 memory controller ensures read and write commands are completed before starting the initialization sequence.

Perform the following steps to start the initialization sequence:

1.Set the BOOT_UNLOCK bit in the SDRAM configuration register (SDCFG).

2.Write a 0 to the BOOT_UNLOCK bit along with the desired value for the DDR_DRIVE bit.

3.Program the rest of the SDCFG to the desired value with the TIMUNLOCK bit set (unlocked).

4.Program the SDRAM timing 1 register (SDTIM1) and SDRAM timing register 2 (SDTIM2) with the value needed to meet the DDR2 SDRAM device timings.

5.Program the REFRESH_RATE bits in the SDRAM refresh control register (SDRFC) to a value that meets the refresh requirements of the DDR2 SDRAM device.

6.Program SDCFG with the desired value and the TIMUNLOCK bit cleared (locked).

7.Program the read latency (RL) bit in the DDR2 memory controller control register (DMCCTL) to the desired value.

2.12Interrupt Support

The DDR2 memory controller does not generate any interrupts.

2.13 EDMA Event Support

The DDR2 memory controller is a DMA slave peripheral and therefore does not generate EDMA events. Data read and write requests may be made directly by masters including the EDMA controller.

2.14 Emulation Considerations

The DDR2 memory controller will remain fully functional during emulation halts to allow emulation access to external memory.

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DSP DDR2 Memory Controller

SPRUF85 –October 2007

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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Data Manual Reference GuidesRelated Documents From Texas Instruments Related Documents From Texas Instruments Functional Block Diagram FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Clock Control Signal DescriptionsMemory Map DDR2 Memory Controller Signal Descriptions Pin DescriptionDDR2 Sdram Commands Truth Table for DDR2 Sdram CommandsCommand Function Protocol DescriptionsMode Register Set MRS and Emrs Refresh ModeDdrclk MRS/EMRS Ddrcke Ddrcs Ddrras Ddrcas Ddrwe COLActivation Actv Ddrcs Ddrras Ddrcas DdrweDcab Command Deactivation Dcab and DeacRead Command DDR2 Read CommandWrite WRT Command Memory Width and Byte AlignmentAddressable Memory Ranges Memory Width Maximum Addressable BytesBank Configuration Register Fields for Address Mapping Address MappingBit Field Bit Value Bit Description IbankLogical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Interface DDR2 Memory Controller Fifo DescriptionDDR2 Memory Controller Fifo Block Diagram Command Ordering and Scheduling, Advanced ConceptCommand Starvation Refresh Scheduling Possible Race ConditionRefresh Urgency Levels Urgency Level DescriptionReset Considerations Self-Refresh ModeReset Sources 11.1 DDR2 Sdram Device Mode Register Configuration Values DDR2 Sdram Mode Register ConfigurationDDR2 Sdram Extended Mode Register 1 Configuration 11 DDR2 Sdram Memory Initialization11.2 DDR2 Sdram Initialization After Reset 11.3 DDR2 Sdram Initialization After Register ConfigurationInterrupt Support Edma Event SupportUsing the DDR2 Memory Controller Connecting the DDR2 Memory Controller to DDR2 SdramConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Programming the Sdram Configuration Register Sdcfg Sdcfg ConfigurationProgramming the Sdram Refresh Control Register Sdrfc Function SelectionDDR2 Memory Refresh Specification Sdrfc ConfigurationConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 SDTIM1 ConfigurationSDTIM2 Configuration Dmcctl ConfigurationDDR2 Sdram Data Register Field Sheet Parameter Name DescriptionDDR2 Memory Controller Registers Offset Acronym Register DescriptionModule ID and Revision Register Midr DDR2 Memory Controller Status Register DmcstatModule ID and Revision Register Midr Field Descriptions Bit Field Value DescriptionSdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field DescriptionsSdram Configuration Register Sdcfg Field Descriptions Sdram Refresh Control Register Sdrfc Sdram Refresh Control Register Sdrfc Field DescriptionsSdram Timing 1 Register SDTIM1 Sdram Timing 1 Register SDTIM1 Field DescriptionsTrfc TRP Trcd TWR Tras TRC TrrdDDR2 memory data sheet. Calculate using this formula Sdram Timing 2 Register SDTIM2 Sdram Timing 2 Register SDTIM2 Field DescriptionsTodt Tsxnr Tsxrd Trtp TckeBurst Priority Register Bprio Field Descriptions Burst Priority Register BprioPrioraise DDR2 Memory Controller Control Register Dmcctl ReseDSP Products ApplicationsRfid
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