Texas Instruments TMS320C6452 DSP manual 11 DDR2 Sdram Memory Initialization

Page 27

www.ti.com

Peripheral Architecture

2.11 DDR2 SDRAM Memory Initialization

DDR2 SDRAM devices contain mode and extended mode registers that configure the mode of operation for the device. These registers control parameters such as burst type, burst length, and CAS latency. The DDR2 memory controller programs the mode and extended mode registers of the DDR2 memory by issuing MRS and EMRS commands during the initialization sequence described in Section 2.11.2 and Section 2.11.3. The initialization sequence performed by the DDR2 memory controller is compliant with the JESDEC79-2A specification.

The DDR2 memory controller performs the initialization sequence under the following conditions:

∙Automatically following a hard or soft reset, see Section 2.11.2.

∙Following a write to the two least-significant bytes in the SDRAM configuration register (SDCFG); see Section 2.11.3.

At the end of the initialization sequence, the DDR2 memory controller performs an auto-refresh cycle, leaving the DDR2 memory controller in an idle state with all banks deactivated.

When the initialization section is started automatically after a hard or soft reset, commands and data stored in the DDR2 memory controller FIFOs are lost. However, when the initialization sequence is initiated by a write to the two least-significant bytes in SDCFG, data and commands stored in the DDR2 memory controller FIFOs are not lost and the DDR2 memory controller ensures read and write commands are completed before starting the initialization sequence.

2.11.1DDR2 SDRAM Device Mode Register Configuration Values

The DDR2 memory controller initializes the mode register and extended mode register 1 of the memory device with the values shown on Table 9 and Table 10. The DDR2 SDRAM extended mode registers 2 and 3 are configured with a value of 0h.

Table 9. DDR2 SDRAM Mode Register Configuration

Mode

Mode Register

 

 

Register Bit

Field

Init Value

Description

12

Power-down Mode

0

Active power-down exit time bit. Configured for Fast exit.

11-9

Write Recovery

SDTIM1.T_WR

Write recovery bits for auto-precharge. Initialized using the

 

 

 

T_WR bits of the SDRAM timing 1 register (SDTIM1).

8

DLL Reset

0

DLL reset bits. DLL is not in reset.

7

Mode

0

Operating mode bit. Normal operating mode is always

 

 

 

selected.

6-4

CAS Latency

SDCFG.CL

CAS latency bits. Initialized using the CL bits of the SDRAM

 

 

 

configuration register (SDCFG).

3

Burst Type

0

Burst type bits. Sequential burst mode is always used.

2-0

Burst Length

3h

Bust length bits. A burst length of 8 is always used.

Table 10. DDR2 SDRAM Extended Mode Register 1 Configuration

Mode

Mode Register

 

 

 

Register Bit

Field

Init Value

Description

 

12

Output Buffer Enable

0

Output buffer enable bits. Output buffer is always enabled.

 

11

RDQS Enable

0

RDQS enable bits. Always initialized to 0 (RDQS signals

 

 

 

 

disabled.)

 

10

DQS enable

0

DQS enable bit. Always initialized to 0 (DQS signals

 

 

 

 

enabled.)

 

9-7

OCD Operation

0h

Off-chip driver impedance calibration bits. This bit is always

 

 

 

initialized to 0h.

 

6

ODT Value (Rtt)

0

On-die termination effective resistance (Rtt) bit. Together

 

 

 

 

with bit 2, this bit selects the value for Rtt as 75Ω.

 

5-3

Additive Latency

0h

Additive latency bits. Always initialized to 0h (no additive

 

 

 

 

latency).

 

SPRUF85 –October 2007

 

DSP DDR2 Memory Controller

27

Submit Documentation Feedback

 

 

 

Page 26 Page 28
Image 27
Page 26 Page 28
Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Reference Guides Data ManualRelated Documents From Texas Instruments Related Documents From Texas Instruments Features Functional Block DiagramPurpose of the Peripheral Industry Standards Compliance Statement Signal Descriptions Clock ControlMemory Map Pin Description DDR2 Memory Controller Signal DescriptionsProtocol Descriptions DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Command FunctionCOL Mode Register Set MRS and EmrsRefresh Mode Ddrclk MRS/EMRS Ddrcke Ddrcs Ddrras Ddrcas DdrweDdrcs Ddrras Ddrcas Ddrwe Activation ActvDeactivation Dcab and Deac Dcab CommandDDR2 Read Command Read CommandMemory Width Maximum Addressable Bytes Write WRT CommandMemory Width and Byte Alignment Addressable Memory RangesIbank Bank Configuration Register Fields for Address MappingAddress Mapping Bit Field Bit Value Bit DescriptionLogical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Fifo Description DDR2 Memory Controller InterfaceCommand Ordering and Scheduling, Advanced Concept DDR2 Memory Controller Fifo Block DiagramCommand Starvation Urgency Level Description Refresh SchedulingPossible Race Condition Refresh Urgency LevelsSelf-Refresh Mode Reset ConsiderationsReset Sources 11 DDR2 Sdram Memory Initialization 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Mode Register Configuration DDR2 Sdram Extended Mode Register 1 ConfigurationEdma Event Support 11.2 DDR2 Sdram Initialization After Reset11.3 DDR2 Sdram Initialization After Register Configuration Interrupt SupportConnecting the DDR2 Memory Controller to DDR2 Sdram Using the DDR2 Memory ControllerConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Function Selection Programming the Sdram Configuration Register SdcfgSdcfg Configuration Programming the Sdram Refresh Control Register SdrfcSDTIM1 Configuration DDR2 Memory Refresh SpecificationSdrfc Configuration Configuring Sdram Timing Registers SDTIM1 and SDTIM2Name Description SDTIM2 ConfigurationDmcctl Configuration DDR2 Sdram Data Register Field Sheet ParameterOffset Acronym Register Description DDR2 Memory Controller RegistersBit Field Value Description Module ID and Revision Register MidrDDR2 Memory Controller Status Register Dmcstat Module ID and Revision Register Midr Field DescriptionsSdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register SdcfgSdram Configuration Register Sdcfg Field Descriptions Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Refresh Control Register SdrfcTras TRC Trrd Sdram Timing 1 Register SDTIM1Sdram Timing 1 Register SDTIM1 Field Descriptions Trfc TRP Trcd TWRDDR2 memory data sheet. Calculate using this formula Tsxrd Trtp Tcke Sdram Timing 2 Register SDTIM2Sdram Timing 2 Register SDTIM2 Field Descriptions Todt TsxnrBurst Priority Register Bprio Burst Priority Register Bprio Field DescriptionsPrioraise Rese DDR2 Memory Controller Control Register DmcctlProducts Applications DSPRfid
Top Page Image Contents