Texas Instruments TMS320C6452 DSP manual DDR2 Memory Controller Registers

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DDR2 Memory Controller Registers

4DDR2 Memory Controller Registers

Table 17 lists the memory-mapped registers for the DDR2 memory controller. See the device-specific data manual for the memory address of these registers.

Table 17. DDR2 Memory Controller Registers

Offset	Acronym	Register Description	Section
00h	MIDR	Module ID and Revision Register	Section 4.1
04h	DMCSTAT	DDR2 Memory Controller Status Register	Section 4.2
08h	SDCFG	SDRAM Configuration Register	Section 4.3
0Ch	SDRFC	SDRAM Refresh Control Register	Section 4.4
10h	SDTIM1	SDRAM Timing 1 Register	Section 4.5
14h	SDTIM2	SDRAM Timing 2 Register	Section 4.6
20h	BPRIO	Burst Priority Register	Section 4.7
E4h	DMCCTL	DDR2 Memory Controller Control Register	Section 4.8

36	DSP DDR2 Memory Controller	SPRUF85 –October 2007
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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Data Manual Reference GuidesRelated Documents From Texas Instruments Related Documents From Texas Instruments Features Functional Block DiagramPurpose of the Peripheral Industry Standards Compliance Statement Signal Descriptions Clock ControlMemory Map DDR2 Memory Controller Signal Descriptions Pin DescriptionDDR2 Sdram Commands Truth Table for DDR2 Sdram CommandsCommand Function Protocol DescriptionsMode Register Set MRS and Emrs Refresh ModeDdrclk MRS/EMRS Ddrcke Ddrcs Ddrras Ddrcas Ddrwe COLActivation Actv Ddrcs Ddrras Ddrcas DdrweDcab Command Deactivation Dcab and DeacRead Command DDR2 Read CommandWrite WRT Command Memory Width and Byte AlignmentAddressable Memory Ranges Memory Width Maximum Addressable BytesBank Configuration Register Fields for Address Mapping Address MappingBit Field Bit Value Bit Description IbankLogical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Interface DDR2 Memory Controller Fifo DescriptionDDR2 Memory Controller Fifo Block Diagram Command Ordering and Scheduling, Advanced ConceptCommand Starvation Refresh Scheduling Possible Race ConditionRefresh Urgency Levels Urgency Level DescriptionSelf-Refresh Mode Reset ConsiderationsReset Sources 11.1 DDR2 Sdram Device Mode Register Configuration Values DDR2 Sdram Mode Register ConfigurationDDR2 Sdram Extended Mode Register 1 Configuration 11 DDR2 Sdram Memory Initialization11.2 DDR2 Sdram Initialization After Reset 11.3 DDR2 Sdram Initialization After Register ConfigurationInterrupt Support Edma Event SupportUsing the DDR2 Memory Controller Connecting the DDR2 Memory Controller to DDR2 SdramConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Programming the Sdram Configuration Register Sdcfg Sdcfg ConfigurationProgramming the Sdram Refresh Control Register Sdrfc Function SelectionDDR2 Memory Refresh Specification Sdrfc ConfigurationConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 SDTIM1 ConfigurationSDTIM2 Configuration Dmcctl ConfigurationDDR2 Sdram Data Register Field Sheet Parameter Name DescriptionDDR2 Memory Controller Registers Offset Acronym Register DescriptionModule ID and Revision Register Midr DDR2 Memory Controller Status Register DmcstatModule ID and Revision Register Midr Field Descriptions Bit Field Value DescriptionSdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field DescriptionsSdram Configuration Register Sdcfg Field Descriptions Sdram Refresh Control Register Sdrfc Sdram Refresh Control Register Sdrfc Field DescriptionsSdram Timing 1 Register SDTIM1 Sdram Timing 1 Register SDTIM1 Field DescriptionsTrfc TRP Trcd TWR Tras TRC TrrdDDR2 memory data sheet. Calculate using this formula Sdram Timing 2 Register SDTIM2 Sdram Timing 2 Register SDTIM2 Field DescriptionsTodt Tsxnr Tsxrd Trtp TckeBurst Priority Register Bprio Burst Priority Register Bprio Field DescriptionsPrioraise DDR2 Memory Controller Control Register Dmcctl ReseProducts Applications DSPRfid