Texas Instruments TMS320C6452 DSP manual Industry Standards Compliance Statement

Page 10

Introduction

EMIFA

DDR2 memory

controller

PLL2

Other peripherals

EDMA

controller

Boot

configuration

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Figure 1. DDR2 Memory Controller Block Diagram

 

 

 

 

L1P

 

 

 

 

 

 

 

 

 

cache/SRAM

 

 

 

 

 

 

 

L2 memory

L1 program memory controller

 

 

Advanced

 

 

controller

Cache control

 

 

 

event

 

 

 

 

 

 

triggering

 

 

 

Bandwidth management

 

 

 

memory

Cache

 

 

(AET)

 

control

Memory protection

 

 

 

 

 

Bandwidth

 

 

 

 

 

 

 

 

resource

L2

management

C64x+ CPU

 

 

 

 

 

 

 

 

 

 

 

 

 

Memory

IDMA

 

Instruction fetch

 

 

protection

 

SPLOOP buffer

 

 

central

 

 

 

 

 

 

 

 

 

16/32−bit instruction dispatch

 

 

 

 

 

Instruction decode

 

 

 

 

 

Data path A

 

 

Data path B

 

Switched

 

External

 

 

 

 

 

 

 

 

 

 

 

 

 

 

memory

L1

S1

M1

D1

D2

M2

S2

L2

 

controller

 

 

 

 

 

 

 

 

 

 

Configuration

 

 

 

 

 

 

 

 

 

 

 

Register file A

 

 

Register file B

 

 

 

registers

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Master

 

 

 

 

 

 

 

 

 

 

DMA

L1 data memory controller

 

 

Interrupt

 

 

 

 

 

 

 

Slave

Cache control

 

 

and exception

 

 

DMA

 

 

 

controller

 

 

Memory protection

 

 

 

 

 

Power control

 

 

 

 

 

 

 

Bandwidth management

 

 

 

 

 

 

 

 

PLL2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L1D

 

 

 

 

 

 

 

 

 

cache/SRAM

 

 

 

 

 

1.4Industry Standard(s) Compliance Statement

The DDR2 memory controller is compliant with the JESD79D-2A DDR2 SDRAM standard with the exception of the On Die Termination (ODT) feature. The DSP does not include any on-die terminating resistors. Furthermore, the on-die terminating resistors of the DDR2 SDRAM device must be disabled by tying the ODT input pin of the DDR2 SDRAM memory to ground.

10

DSP DDR2 Memory Controller

SPRUF85 –October 2007

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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Data Manual Reference GuidesRelated Documents From Texas Instruments Related Documents From Texas Instruments Functional Block Diagram FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Clock Control Signal DescriptionsMemory Map DDR2 Memory Controller Signal Descriptions Pin DescriptionCommand Function DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Protocol DescriptionsDdrclk MRS/EMRS Ddrcke Ddrcs Ddrras Ddrcas Ddrwe Mode Register Set MRS and EmrsRefresh Mode COLActivation Actv Ddrcs Ddrras Ddrcas DdrweDcab Command Deactivation Dcab and DeacRead Command DDR2 Read CommandAddressable Memory Ranges Write WRT CommandMemory Width and Byte Alignment Memory Width Maximum Addressable BytesBit Field Bit Value Bit Description Bank Configuration Register Fields for Address MappingAddress Mapping IbankLogical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Interface DDR2 Memory Controller Fifo DescriptionDDR2 Memory Controller Fifo Block Diagram Command Ordering and Scheduling, Advanced ConceptCommand Starvation Refresh Urgency Levels Refresh SchedulingPossible Race Condition Urgency Level DescriptionReset Considerations Self-Refresh ModeReset Sources DDR2 Sdram Extended Mode Register 1 Configuration 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Mode Register Configuration 11 DDR2 Sdram Memory InitializationInterrupt Support 11.2 DDR2 Sdram Initialization After Reset11.3 DDR2 Sdram Initialization After Register Configuration Edma Event SupportUsing the DDR2 Memory Controller Connecting the DDR2 Memory Controller to DDR2 SdramConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Programming the Sdram Refresh Control Register Sdrfc Programming the Sdram Configuration Register SdcfgSdcfg Configuration Function SelectionConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 DDR2 Memory Refresh SpecificationSdrfc Configuration SDTIM1 ConfigurationDDR2 Sdram Data Register Field Sheet Parameter SDTIM2 ConfigurationDmcctl Configuration Name DescriptionDDR2 Memory Controller Registers Offset Acronym Register DescriptionModule ID and Revision Register Midr Field Descriptions Module ID and Revision Register MidrDDR2 Memory Controller Status Register Dmcstat Bit Field Value DescriptionSdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field DescriptionsSdram Configuration Register Sdcfg Field Descriptions Sdram Refresh Control Register Sdrfc Sdram Refresh Control Register Sdrfc Field DescriptionsTrfc TRP Trcd TWR Sdram Timing 1 Register SDTIM1Sdram Timing 1 Register SDTIM1 Field Descriptions Tras TRC TrrdDDR2 memory data sheet. Calculate using this formula Todt Tsxnr Sdram Timing 2 Register SDTIM2Sdram Timing 2 Register SDTIM2 Field Descriptions Tsxrd Trtp TckeBurst Priority Register Bprio Field Descriptions Burst Priority Register BprioPrioraise DDR2 Memory Controller Control Register Dmcctl ReseDSP Products ApplicationsRfid
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