Texas Instruments TMS320C6452 DSP manual Connecting to Two 16-Bit DDR2 Sdram Devices

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Using the DDR2 Memory Controller

Figure 17. Connecting to Two 16-Bit DDR2 SDRAM Devices

DDR_CLK

DDR_CLK

DDR2 DDR_CKE memory DDR_CS

controller DDR_WE DDR_RAS DDR_CAS DDR_DQM0 DDR_DQM1 DDR_DQS0 DDR_DQS0 DDR_DQS1 DDR_DQS1 DDR_BA[2:0] DDR_A[13:0] DDR_D[15:0] DDR_DQM2 DDR_DQM3 DDR_DQS2 DDR_DQS2 DDR_DQS3 DDR_DQS3 DDR_D[31:16] DDR_ODT0 DDR_ODT1 DDR_DQGATE0(A) DDR_DQGATE1(A) DDR_DQGATE2(A) DDR_DQGATE3(A)

VREF

CK

CK

CKE

CS

WE

RAS DDR2

CAS memory x16−bit

LDM

UDM

LDQS

LDQS

UDQS

UDQS

BA[2:0]

A[12:0]

DQ[15:0]

ODT

VREF

CK

CK

CKE

CS

WE

RAS DDR2

CAS memory x16−bit

LDM

UDM

LDQS

LDQS

UDQS

UDQS

BA[2:0]

A[12:0]

DQ[15:0]

ODT

VREF

AThese pins are used as a timing reference during memory reads. For routing rules, see the device-specific data manual.

30	DSP DDR2 Memory Controller	SPRUF85 –October 2007
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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Data Manual Reference GuidesRelated Documents From Texas Instruments Related Documents From Texas Instruments Features Functional Block DiagramPurpose of the Peripheral Industry Standards Compliance Statement Signal Descriptions Clock ControlMemory Map DDR2 Memory Controller Signal Descriptions Pin DescriptionCommand Function DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Protocol DescriptionsDdrclk MRS/EMRS Ddrcke Ddrcs Ddrras Ddrcas Ddrwe Mode Register Set MRS and EmrsRefresh Mode COLActivation Actv Ddrcs Ddrras Ddrcas DdrweDcab Command Deactivation Dcab and DeacRead Command DDR2 Read CommandAddressable Memory Ranges Write WRT CommandMemory Width and Byte Alignment Memory Width Maximum Addressable BytesBit Field Bit Value Bit Description Bank Configuration Register Fields for Address MappingAddress Mapping IbankLogical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Interface DDR2 Memory Controller Fifo DescriptionDDR2 Memory Controller Fifo Block Diagram Command Ordering and Scheduling, Advanced ConceptCommand Starvation Refresh Urgency Levels Refresh SchedulingPossible Race Condition Urgency Level DescriptionSelf-Refresh Mode Reset ConsiderationsReset Sources DDR2 Sdram Extended Mode Register 1 Configuration 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Mode Register Configuration 11 DDR2 Sdram Memory InitializationInterrupt Support 11.2 DDR2 Sdram Initialization After Reset11.3 DDR2 Sdram Initialization After Register Configuration Edma Event SupportUsing the DDR2 Memory Controller Connecting the DDR2 Memory Controller to DDR2 SdramConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Programming the Sdram Refresh Control Register Sdrfc Programming the Sdram Configuration Register SdcfgSdcfg Configuration Function SelectionConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 DDR2 Memory Refresh SpecificationSdrfc Configuration SDTIM1 ConfigurationDDR2 Sdram Data Register Field Sheet Parameter SDTIM2 ConfigurationDmcctl Configuration Name DescriptionDDR2 Memory Controller Registers Offset Acronym Register DescriptionModule ID and Revision Register Midr Field Descriptions Module ID and Revision Register MidrDDR2 Memory Controller Status Register Dmcstat Bit Field Value DescriptionSdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field DescriptionsSdram Configuration Register Sdcfg Field Descriptions Sdram Refresh Control Register Sdrfc Sdram Refresh Control Register Sdrfc Field DescriptionsTrfc TRP Trcd TWR Sdram Timing 1 Register SDTIM1Sdram Timing 1 Register SDTIM1 Field Descriptions Tras TRC TrrdDDR2 memory data sheet. Calculate using this formula Todt Tsxnr Sdram Timing 2 Register SDTIM2Sdram Timing 2 Register SDTIM2 Field Descriptions Tsxrd Trtp TckeBurst Priority Register Bprio Burst Priority Register Bprio Field DescriptionsPrioraise DDR2 Memory Controller Control Register Dmcctl ReseProducts Applications DSPRfid