Pico Communications manual Pico E-15, Release For Hardware Revision D

Release For Hardware Revision D Pico E-15Page Product Overview IO Connectivity Pico E-15 Quick Reference DatasheetStandard Part Number Standard Part NumbersMilitary version is available which includes System Architecture Minimum Nominal Maximum Pico E-15 Electrical SpecificationField Programmable Gate Array PPC405x3 Processor Introduction PowerPC ProcessorCpld Resources Xilinx Cpld Website Cpld TurboLoaderFlash Memory DDR2 Sdram Memory RAMParameter Value EDK Value 133 MHz 333 MHz RAM Timing and Parameter InformationElectrical Specifications Minimum Nominal Maximum Temperature SensorSleep Controller Ethernet Resources Tri-Mode Ethernet InterfaceHI-Z Digital Peripheral InterfaceHigh Speed Analog to Digital Converters VDC Low pass filter range is customizable via special order High Speed Digital to Analog Converters Page Video Digitizer External Connections Composite Mode Video Digitizer External Connections Svideo ModeVideo Digitizer Video Digitizer Resources TVP5150AM1 HomepageCardBus / Digital Bus Interface Electrical Specifications DC Minimum Nominal MaximumPcmcia Interface Resources Pcmcia Website PCI SIG Website Device Jtag Debug InterfaceInstruction register bit length PSoC Debug Interface Connector Information Appendix a Peripheral I/O Connector InformationPeripheral I/O Connector Pinout Peripheral Connector Drawing FCI Appendix B CardBus Connector InformationCardBus Interface Schematic Pcicpar CardBus Connector PinoutPCICAD17 Fpga Pinout Appendix C Fpga PinoutCAD0 AA4 ETHERTX1 FLASHD11 RAMDQ5 Vdcfid Cpld Pinout Appendix D Cpld PinoutPSoC Pinout Appendix E PSoC PinoutStandard Part Number Listing Appendix F Standard Part Number ListingDevice Part Number Website Appendix G Errata Appendix H Fpga Performance Enhancements Revision History Legal Notices