Pico Communications E-15 manual Tri-Mode Ethernet Interface, Ethernet Resources

Page 16

16

Tri-Mode Ethernet Interface

The Pico E-15 features the Marvell Alaska series 88E1111 tri-mode Ethernet transceiver. Combined with the on-FPGA MAC (Middle access controller) a complete Ethernet solution is offered. Communication between the MAC and PHY takes place over an industry standard MII/GMII interface.

The Ethernet transceiver features 10/100/1000 full/half duplex operation. It will automatically configure the physical interface on the fly for crossover or straight through operation. The PHY can even automatically correct for common wiring mistakes. The PHY has a built in Time Domain Reflectometer which can diagnose cable problems and pinpoint their distance away from the transceiver.

The Ethernet interface on the Pico is magnetic-less allowing high speed, low power digital interconnect directly to Ethernet backplanes. DO NOT directly connect the Ethernet interface to a hub or switch without a magnetic isolation module.

The Marvell 88E1111 is the only user-accessible chip on the Pico E-15 that requires an NDA for access to the datasheets. If you are interested in some of the advanced features not supported by the native driver, contact Pico Computing for assistance in obtaining an NDA from Marvell. Users are advised not to contact Marvell directly.

Ethernet Resources:

Marvell 88E1111 Webpage

http://www.marvell.com/products/transceivers/singleport/88e1111.jsp

Pico E-15 Hardware Reference

www.picocomputing.com

Pico Computing

 

(206) 283-2178

150 Nickerson Street. Suite 311

 

 

Seattle, WA 98109

Image 16
Contents Pico E-15 Release For Hardware Revision DPage Product Overview Pico E-15 Quick Reference Datasheet IO ConnectivityStandard Part Number Standard Part NumbersMilitary version is available which includes System Architecture Pico E-15 Electrical Specification Minimum Nominal MaximumField Programmable Gate Array PowerPC Processor PPC405x3 Processor IntroductionCpld TurboLoader Cpld Resources Xilinx Cpld WebsiteFlash Memory RAM DDR2 Sdram MemoryRAM Timing and Parameter Information Parameter Value EDK Value 133 MHz 333 MHzTemperature Sensor Electrical Specifications Minimum Nominal MaximumSleep Controller Tri-Mode Ethernet Interface Ethernet ResourcesDigital Peripheral Interface HI-ZHigh Speed Analog to Digital Converters VDC Low pass filter range is customizable via special order High Speed Digital to Analog Converters Page Video Digitizer External Connections Svideo Mode Video Digitizer External Connections Composite ModeVideo Digitizer Video Digitizer Resources TVP5150AM1 HomepageCardBus / Digital Bus Interface Electrical Specifications DC Minimum Nominal MaximumPcmcia Interface Resources Pcmcia Website PCI SIG Website Device Jtag Debug InterfaceInstruction register bit length PSoC Debug Interface Connector Information Appendix a Peripheral I/O Connector InformationPeripheral I/O Connector Pinout Peripheral Connector Drawing Appendix B CardBus Connector Information FCICardBus Interface Schematic CardBus Connector Pinout PcicparPCICAD17 Appendix C Fpga Pinout Fpga PinoutCAD0 AA4 ETHERTX1 FLASHD11 RAMDQ5 Vdcfid Appendix D Cpld Pinout Cpld PinoutAppendix E PSoC Pinout PSoC PinoutStandard Part Number Listing Appendix F Standard Part Number ListingDevice Part Number Website Appendix G Errata Appendix H Fpga Performance Enhancements Revision History Legal Notices