Pico Communications E-15 manual ETHERTX1

Page 36

36

ETHER_TX1

F20

TX Data #1

O

LVCMOS18

Float

4mA

ETHER_TX2

E21

TX Data #2

O

LVCMOS18

Float

4mA

ETHER_TX3

C23

TX Data #3

O

LVCMOS18

Float

4mA

ETHER_TX4

C21

TX Data #4

O

LVCMOS18

Float

4mA

ETHER_TX5

D21

TX Data #5

O

LVCMOS18

Float

4mA

ETHER_TX6

D23

TX Data #6

O

LVCMOS18

Float

4mA

ETHER_TX7

E23

TX Data #7

O

LVCMOS18

Float

4mA

ETHER_TX_CLK

D19

TX Clock

O

LVCMOS18

Float

4mA

ETHER_TX_CTL

C19

TX Control (Enable)

O

LVCMOS18

Float

4mA

ETHER_TX_ER

E17

TX Error

O

LVCMOS18

Float

4mA

F\L\A\S\H\_\B\Y\T\E\

AC17

16 / 8 Bit Mode Select

O

LVCMOS18

Float

4mA

F\L\A\S\H\_\C\E\

J16

Chip Enable

O

LVCMOS18

Float

4mA

F\L\A\S\H\_\O\E\

H13

Output Enable

O

LVCMOS18

Float

4mA

F\L\A\S\H\_\W\E\

AD19

Write Enable

O

LVCMOS18

Float

4mA

FLASH_A0

U17

Address # 0

I/O

LVCMOS18

Float

4mA

FLASH_A1

U15

Address # 1

I/O

LVCMOS18

Float

4mA

FLASH_A2

V11

Address # 2

I/O

LVCMOS18

Float

4mA

FLASH_A3

AC18

Address # 3

I/O

LVCMOS18

Float

4mA

 

FLASH_A4

Y11

Address # 4

I/O

LVCMOS18

Float

4mA

 

FLASH_A5

V16

Address # 5

I/O

LVCMOS18

Float

4mA

 

FLASH_A6

W11

Address # 6

I/O

LVCMOS18

Float

4mA

 

FLASH_A7

AD18

Address # 7

I/O

LVCMOS18

Float

4mA

 

FLASH_A8

AB19

Address # 8

I/O

LVCMOS18

Float

4mA

 

FLASH_A9

AD20

Address # 9

I/O

LVCMOS18

Float

4mA

 

FLASH_A10

AB20

Address # 10

I/O

LVCMOS18

Float

4mA

 

FLASH_A11

Y15

Address # 11

I/O

LVCMOS18

Float

4mA

FLASH_A12

AC22

Address # 12

I/O

LVCMOS18

Float

4mA

FLASH_A13

AB21

Address # 13

I/O

LVCMOS18

Float

4mA

FLASH_A14

AA15

Address # 14

I/O

LVCMOS18

Float

4mA

FLASH_A15

AA17

Address # 15

I/O

LVCMOS18

Float

4mA

FLASH_A16

AD16

Address # 16

I/O

LVCMOS18

Float

4mA

FLASH_A17

Y12

Address # 17

I/O

LVCMOS18

Float

4mA

FLASH_A18

AA20

Address # 18

I/O

LVCMOS18

Float

4mA

FLASH_A19

Y16

Address # 19

I/O

LVCMOS18

Float

4mA

FLASH_A20

U16

Address # 20

I/O

LVCMOS18

Float

4mA

FLASH_A21

W16

Address # 21

I/O

LVCMOS18

Float

4mA

FLASH_A22

AD23

Address # 22

I/O

LVCMOS18

Float

4mA

FLASH_A23

AB15

Address # 23

I/O

LVCMOS18

Float

4mA

FLASH_A24

AB16

Address # 24

I/O

LVCMOS18

Float

4mA

FLASH_D0

V12

Data #0

I/O

LVCMOS18

Float

4mA

FLASH_D1

V13

Data #1

I/O

LVCMOS18

Float

4mA

FLASH_D2

V14

Data #2

I/O

LVCMOS18

Float

4mA

FLASH_D3

U14

Data #3

I/O

LVCMOS18

Float

4mA

FLASH_D4

W13

Data #4

I/O

LVCMOS18

Float

4mA

FLASH_D5

Y13

Data #5

I/O

LVCMOS18

Float

4mA

FLASH_D6

W14

Data #6

I/O

LVCMOS18

Float

4mA

FLASH_D7

W15

Data #7

I/O

LVCMOS18

Float

4mA

FLASH_D8

T17

Data #8

I/O

LVCMOS18

Float

4mA

FLASH_D9

J14

Data #9

I/O

LVCMOS18

Float

4mA

FLASH_D10

K12

Data #10

I/O

LVCMOS18

Float

4mA

Pico E-15 Hardware Reference

www.picocomputing.com

Pico Computing

 

(206) 283-2178

150 Nickerson Street. Suite 311

 

 

Seattle, WA 98109

Image 36
Contents Pico E-15 Release For Hardware Revision DPage Product Overview Pico E-15 Quick Reference Datasheet IO ConnectivityStandard Part Numbers Standard Part NumberMilitary version is available which includes System Architecture Pico E-15 Electrical Specification Minimum Nominal MaximumField Programmable Gate Array PowerPC Processor PPC405x3 Processor IntroductionCpld TurboLoader Cpld Resources Xilinx Cpld WebsiteFlash Memory RAM DDR2 Sdram MemoryRAM Timing and Parameter Information Parameter Value EDK Value 133 MHz 333 MHzTemperature Sensor Electrical Specifications Minimum Nominal MaximumSleep Controller Tri-Mode Ethernet Interface Ethernet ResourcesDigital Peripheral Interface HI-ZHigh Speed Analog to Digital Converters VDC Low pass filter range is customizable via special order High Speed Digital to Analog Converters Page Video Digitizer External Connections Svideo Mode Video Digitizer External Connections Composite ModeVideo Digitizer Video Digitizer Resources TVP5150AM1 HomepageElectrical Specifications DC Minimum Nominal Maximum CardBus / Digital Bus InterfacePcmcia Interface Resources Pcmcia Website PCI SIG Website Jtag Debug Interface DeviceInstruction register bit length PSoC Debug Interface Appendix a Peripheral I/O Connector Information Connector InformationPeripheral I/O Connector Pinout Peripheral Connector Drawing Appendix B CardBus Connector Information FCICardBus Interface Schematic CardBus Connector Pinout PcicparPCICAD17 Appendix C Fpga Pinout Fpga PinoutCAD0 AA4 ETHERTX1 FLASHD11 RAMDQ5 Vdcfid Appendix D Cpld Pinout Cpld PinoutAppendix E PSoC Pinout PSoC PinoutAppendix F Standard Part Number Listing Standard Part Number ListingDevice Part Number Website Appendix G Errata Appendix H Fpga Performance Enhancements Revision History Legal Notices