Pico Communications E-15 manual Field Programmable Gate Array

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Field Programmable Gate Array

The core of the Pico E-15 is a high performance Virtex-4 FPGA. Included in the FPGA are the FPGA Fabric, an optional PowerPC ™ processor, ultra high-speed DSP slices and RAM.

FPGA Fabric:

The “Fabric” of an FPGA comprises an array of logic elements that can be connected in virtually unlimited patterns. These patterns of logic elements can be used to perform basic mathematical functions such as addition and subtraction, or can be grouped together to perform complex functions like Fast Fourier Transforms. Logic elements can even be connected to create a custom soft processor.

The advantage of the FPGA is that the internal logic can be optimized for a specific application. FPGAs are also able to execute operations in parallel, not being limited by sequential execution like a traditional processor. FPGA operations can be executed in a parallel, pipelined or even an asynchronous manner. The FPGA allows incredible application speed with very low power consumption. Your imagination is really the limit.

DSP Slice:

Embedded within the FPGA are special areas that are designed to facilitate high speed “digital signal processing.” These areas are called DSP slices. The DSP slice can be configured in a variety of different ways. For example, one DSP slice can be configured to be one tap of an FIR filter. DSP slices are fully pipelined and feature incredible speed. When configured for FIR filtering the DSP slice has a guaranteed performance of 500MHz with a latency of one cycle. An 18x18 multiply and accumulate also runs at 250MHz with a latency of two cycles. Smaller data widths allow higher clock speeds.

FPGA Resources:

Free FPGA Cores

http://www.opencores.org

 

 

 

 

Encryption Cores

http://www.openciphers.org

 

Virtex-4 Website

http://www.xilinx.com/virtex4

 

Pico E-15 Hardware Reference

www.picocomputing.com

Pico Computing

 

(206) 283-2178

150 Nickerson Street. Suite 311

 

 

Seattle, WA 98109

Image 8 Contents
Pico E-15 Release For Hardware Revision DPage Product Overview Pico E-15 Quick Reference Datasheet IO ConnectivityMilitary version is available which includes Standard Part NumbersStandard Part Number System Architecture Pico E-15 Electrical Specification Minimum Nominal MaximumField Programmable Gate Array PowerPC Processor PPC405x3 Processor IntroductionCpld TurboLoader Cpld Resources Xilinx Cpld WebsiteFlash Memory RAM DDR2 Sdram MemoryRAM Timing and Parameter Information Parameter Value EDK Value 133 MHz 333 MHzTemperature Sensor Electrical Specifications Minimum Nominal MaximumSleep Controller Tri-Mode Ethernet Interface Ethernet ResourcesDigital Peripheral Interface HI-ZHigh Speed Analog to Digital Converters VDC Low pass filter range is customizable via special order High Speed Digital to Analog Converters Page Video Digitizer External Connections Svideo Mode Video Digitizer External Connections Composite ModeVideo Digitizer Video Digitizer Resources TVP5150AM1 HomepagePcmcia Interface Resources Pcmcia Website PCI SIG Website Electrical Specifications DC Minimum Nominal MaximumCardBus / Digital Bus Interface Instruction register bit length Jtag Debug InterfaceDevice PSoC Debug Interface Peripheral I/O Connector Pinout Appendix a Peripheral I/O Connector InformationConnector Information Peripheral Connector Drawing Appendix B CardBus Connector Information FCICardBus Interface Schematic CardBus Connector Pinout PcicparPCICAD17 Appendix C Fpga Pinout Fpga PinoutCAD0 AA4 ETHERTX1 FLASHD11 RAMDQ5 Vdcfid Appendix D Cpld Pinout Cpld PinoutAppendix E PSoC Pinout PSoC PinoutDevice Part Number Website Appendix F Standard Part Number ListingStandard Part Number Listing Appendix G Errata Appendix H Fpga Performance Enhancements Revision History Legal Notices
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