Pico Communications E-15 manual Flash Memory

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Flash Memory

The Pico E-15 comes equipped with at least 64MB of Flash ROM. The Flash ROM is divided into 512 sectors that can be erased independently. Most of the space on the ROM is reserved for the user.

The Flash ROM’s address bus can be controlled by either the TurboLoader or the FPGA (but not both). During power-up or reboot, the TurboLoader is in control of the Flash ROM Address bus. At all other times the FPGA is in control of the address bus.

The Flash ROM has a simple, open file system which allows the user to store FPGA images, ELF binary files, or other data. The primary image is used to boot the FPGA initially, and the backup image is only invoked if the primary image fails to load correctly. Executable files are in ELF format and are loaded by a loader within the secondary image. The primary image will either load the secondary image or pause for the PC to access and manage the file system.

Pico E-15 Hardware Reference	www.picocomputing.com	Pico Computing
	(206) 283-2178	150 Nickerson Street. Suite 311
		Seattle, WA 98109

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Contents

Release For Hardware Revision D Pico E-15Page Product Overview IO Connectivity Pico E-15 Quick Reference DatasheetMilitary version is available which includes Standard Part NumbersStandard Part Number System Architecture Minimum Nominal Maximum Pico E-15 Electrical SpecificationField Programmable Gate Array PPC405x3 Processor Introduction PowerPC ProcessorCpld Resources Xilinx Cpld Website Cpld TurboLoaderFlash Memory DDR2 Sdram Memory RAMParameter Value EDK Value 133 MHz 333 MHz RAM Timing and Parameter InformationElectrical Specifications Minimum Nominal Maximum Temperature SensorSleep Controller Ethernet Resources Tri-Mode Ethernet InterfaceHI-Z Digital Peripheral InterfaceHigh Speed Analog to Digital Converters VDC Low pass filter range is customizable via special order High Speed Digital to Analog Converters Page Video Digitizer Resources TVP5150AM1 Homepage Video Digitizer External Connections Svideo ModeVideo Digitizer External Connections Composite Mode Video DigitizerPcmcia Interface Resources Pcmcia Website PCI SIG Website Electrical Specifications DC Minimum Nominal MaximumCardBus / Digital Bus Interface Instruction register bit length Jtag Debug InterfaceDevice PSoC Debug Interface Peripheral I/O Connector Pinout Appendix a Peripheral I/O Connector InformationConnector Information Peripheral Connector Drawing FCI Appendix B CardBus Connector InformationCardBus Interface Schematic Pcicpar CardBus Connector PinoutPCICAD17 Fpga Pinout Appendix C Fpga PinoutCAD0 AA4 ETHERTX1 FLASHD11 RAMDQ5 Vdcfid Cpld Pinout Appendix D Cpld PinoutPSoC Pinout Appendix E PSoC PinoutDevice Part Number Website Appendix F Standard Part Number ListingStandard Part Number Listing Appendix G Errata Appendix H Fpga Performance Enhancements Revision History Legal Notices

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