Pico Communications E-15 manual PCICAD17

Page 32

32

49

P\C\I\_\C\S\T\O\P\

Transfer Halt

50

P\C\I\_C\D\E\V\S\E\L\

Device Select

51

3.3V

3.3V Digital Supply

52

VPP

No Connection

53

P\C\I\_\C\T\R\D\Y\

Target Ready

54

P\C\I\_\C\F\R\A\M\E\

Frame

55

PCI_CAD17

Data / Address 17

56

PCI_CAD19

Data / Address 19

58

P\C\I\_\C\R\S\T\

Reset

59

P\C\I\_\C\S\E\R\R\

System Error

60

P\C\I\_\C\R\E\Q\

Access Request

61

P\C\I\_\C\C\B\E\3\

Byte Enable 3

62

PCI_CAUDIO

Audio

63

PCI_CSTSCHG

Status Change Interrupt

64

PCI_CAD28

Data / Address 28

65

PCI_CAD30

Data / Address 30

66

PCI_CAD31

Data / Address 31

67

GND

Digital Ground

68

GND

Digital Ground

Pico E-15 Hardware Reference

www.picocomputing.com

Pico Computing

 

(206) 283-2178

150 Nickerson Street. Suite 311

 

 

Seattle, WA 98109

Image 32 Contents
Pico E-15 Release For Hardware Revision DPage Product Overview Pico E-15 Quick Reference Datasheet IO ConnectivityMilitary version is available which includes Standard Part NumbersStandard Part Number System Architecture Pico E-15 Electrical Specification Minimum Nominal MaximumField Programmable Gate Array PowerPC Processor PPC405x3 Processor IntroductionCpld TurboLoader Cpld Resources Xilinx Cpld WebsiteFlash Memory RAM DDR2 Sdram MemoryRAM Timing and Parameter Information Parameter Value EDK Value 133 MHz 333 MHzTemperature Sensor Electrical Specifications Minimum Nominal MaximumSleep Controller Tri-Mode Ethernet Interface Ethernet ResourcesDigital Peripheral Interface HI-ZHigh Speed Analog to Digital Converters VDC Low pass filter range is customizable via special order High Speed Digital to Analog Converters Page Video Digitizer External Connections Svideo Mode Video Digitizer External Connections Composite ModeVideo Digitizer Video Digitizer Resources TVP5150AM1 HomepagePcmcia Interface Resources Pcmcia Website PCI SIG Website Electrical Specifications DC Minimum Nominal MaximumCardBus / Digital Bus Interface Instruction register bit length Jtag Debug InterfaceDevice PSoC Debug Interface Peripheral I/O Connector Pinout Appendix a Peripheral I/O Connector InformationConnector Information Peripheral Connector Drawing Appendix B CardBus Connector Information FCICardBus Interface Schematic CardBus Connector Pinout PcicparPCICAD17 Appendix C Fpga Pinout Fpga PinoutCAD0 AA4 ETHERTX1 FLASHD11 RAMDQ5 Vdcfid Appendix D Cpld Pinout Cpld PinoutAppendix E PSoC Pinout PSoC PinoutDevice Part Number Website Appendix F Standard Part Number ListingStandard Part Number Listing Appendix G Errata Appendix H Fpga Performance Enhancements Revision History Legal Notices
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