Pico Communications E-15 manual Appendix a Peripheral I/O Connector Information

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Appendix A – Peripheral I/O Connector Information

Connector Information

Description	Brand	Part Number
Mating Connector	Hirose	NX-32TA-CV1(50)
*Connectors are always in stock at Pico Computing

Peripheral I/O Connector Pinout

1	VIDEO_GND	Analog Video Ground	0V DC – Ground [VIDEO]
2	VIDEO_IN_C	Analog Video Input (Chrominance)	NTSC / CAM / PAL Video
3	VIDEO_IN_Y	Analog Video Input (Luminance)	NTSC / CAM / PAL Video
4	TMS	JTAG Mode Select	LVCMOS-1.8
5	TCK	JTAG Clock	LVCMOS-1.8
6	TDI	JTAG Data In	LVCMOS-1.8
7	TDO	JTAG Data Out	LVCMOS-1.8
8	ANALOG_IN_1+	Differential Analog In #1 +	1.8V Pk-Pk 50 Ohm Analog
9	ANALOG_IN_1-	Differential Analog In #1 -	1.8V Pk-Pk 50 Ohm Analog
10	ETHER_OUT_DA-	Ethernet DA-	IEEE 802.3
11	ETHER_OUT_DA+	Ethernet DA+	IEEE 802.3
12	ETHER_OUT_DD-	Ethernet DD-	IEEE 802.3
13	ETHER_OUT_DD+	Ethernet DD+	IEEE 802.3
14	ETHER_OUT_DC-	Ethernet DC-	IEEE 802.3
15	ETHER_OUT_DC+	Ethernet DC+	IEEE 802.3
16	ETHER_OUT_DB-	Ethernet DB-	IEEE 802.3
17	ETHER_OUT_DB+	Ethernet DB+	IEEE 802.3
18	POWERCTL_R	PSoC Debug Interface Reset	LVTTL-3.3
19	ANALOG_IN_2-	Differential Analog In #2 -	1.8V Pk-Pk 50 Ohm Analog
20	ANALOG_IN_2+	Differential Analog In #2 +	1.8V Pk-Pk 50 Ohm Analog
21	2.5V	2.5V 250mA Max	2.5V DC
22	DIAG_EN_n	Diagnostic Enable	LVCMOS-1.8
23	1.8V	1.8V 250mA Max	1.8V DC
24	POWERCTL_C	PSoC Debug Clock	LVTTL-3.3
25	POWERCTL_D	PSoC Debug Data / WAKEUP	LVTTL-3.3
26	GPIO_1	General Purpose IO #1	LVTTL-3.3
27	GPIO_2	General Putpose IO #2	LVTTL-3.3
28	GND	Digital Ground	0V DC – Ground [DIGITAL]
29	ANALOG_OUT_2+	Differential Analog Out #2 +	1.8V Pk-Pk 50 Ohm Analog
30	ANALOG_OUT_2-	Differential Analog Out #2 -	1.8V Pk-Pk 50 Ohm Analog
31	ANALOG_OUT_1+	Differential Analog Out #1 +	1.8V Pk-Pk 50 Ohm Analog
32	ANALOG_OUT_1-	Differential Analog Out #1 -	1.8V Pk-Pk 50 Ohm Analog

Pico E-15 Hardware Reference	www.picocomputing.com	Pico Computing
	(206) 283-2178	150 Nickerson Street. Suite 311
		Seattle, WA 98109

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Contents Release For Hardware Revision D Pico E-15Page Product Overview IO Connectivity Pico E-15 Quick Reference DatasheetStandard Part Numbers Standard Part NumberMilitary version is available which includes System Architecture Minimum Nominal Maximum Pico E-15 Electrical SpecificationField Programmable Gate Array PPC405x3 Processor Introduction PowerPC ProcessorCpld Resources Xilinx Cpld Website Cpld TurboLoaderFlash Memory DDR2 Sdram Memory RAMParameter Value EDK Value 133 MHz 333 MHz RAM Timing and Parameter InformationElectrical Specifications Minimum Nominal Maximum Temperature SensorSleep Controller Ethernet Resources Tri-Mode Ethernet InterfaceHI-Z Digital Peripheral InterfaceHigh Speed Analog to Digital Converters VDC Low pass filter range is customizable via special order High Speed Digital to Analog Converters Page Video Digitizer Resources TVP5150AM1 Homepage Video Digitizer External Connections Svideo ModeVideo Digitizer External Connections Composite Mode Video DigitizerElectrical Specifications DC Minimum Nominal Maximum CardBus / Digital Bus InterfacePcmcia Interface Resources Pcmcia Website PCI SIG Website Jtag Debug Interface DeviceInstruction register bit length PSoC Debug Interface Appendix a Peripheral I/O Connector Information Connector InformationPeripheral I/O Connector Pinout Peripheral Connector Drawing FCI Appendix B CardBus Connector InformationCardBus Interface Schematic Pcicpar CardBus Connector PinoutPCICAD17 Fpga Pinout Appendix C Fpga PinoutCAD0 AA4 ETHERTX1 FLASHD11 RAMDQ5 Vdcfid Cpld Pinout Appendix D Cpld PinoutPSoC Pinout Appendix E PSoC PinoutAppendix F Standard Part Number Listing Standard Part Number ListingDevice Part Number Website Appendix G Errata Appendix H Fpga Performance Enhancements Revision History Legal Notices