Pico Communications E-15 manual RAM Timing and Parameter Information

Page 13

13

RAM Timing and Parameter Information

Parameter

Value

EDK Value

EDK Value

 

 

133 MHz

333 MHz

Registered

No

0

0

Clock Pairs

1

1

1

Memory Banks

1

1

1

IDELAY Controllers

2

2

2

Differential DQs

Yes

1

1

Open Row Management

No

0

0

On Die Termination

Disabled

0

0

ECC Support

No

0

0

TMRD

2 Clocks

15000

6000

TWR

15 nS

15000

1500

TWTR

7.5 nS

1

3

TRAS

45 nS

45000

45000

TRC

60 nS

60000

60000

TRFC

127.5 nS

12750

12750

TRCD

15 nS

15000

15000

TRRD

10 nS

10000

10000

TRP

15 nS

15000

15000

TREFI

7.8 uS

7800000

7800000

TFAW

37.5

37500

37500

CAS Latency

5 Clocks

5

5

Data Width

32 Bits

32

32

Address Width

13 Bits

13

13

Column Width

10 Bits

10

10

Bank Address Width

3

3

3

Clock Period*

5 nS

7500

3000

*Minimum RAM Speed is 125MHz

 

 

 

Pico E-15 Hardware Reference

www.picocomputing.com

Pico Computing

 

(206) 283-2178

150 Nickerson Street. Suite 311

 

 

Seattle, WA 98109

Image 13 Contents
Release For Hardware Revision D Pico E-15Page Product Overview IO Connectivity Pico E-15 Quick Reference DatasheetStandard Part Number Standard Part NumbersMilitary version is available which includes System Architecture Minimum Nominal Maximum Pico E-15 Electrical SpecificationField Programmable Gate Array PPC405x3 Processor Introduction PowerPC ProcessorCpld Resources Xilinx Cpld Website Cpld TurboLoaderFlash Memory DDR2 Sdram Memory RAMParameter Value EDK Value 133 MHz 333 MHz RAM Timing and Parameter InformationElectrical Specifications Minimum Nominal Maximum Temperature SensorSleep Controller Ethernet Resources Tri-Mode Ethernet InterfaceHI-Z Digital Peripheral InterfaceHigh Speed Analog to Digital Converters VDC Low pass filter range is customizable via special order High Speed Digital to Analog Converters Page Video Digitizer External Connections Composite Mode Video Digitizer External Connections Svideo ModeVideo Digitizer Video Digitizer Resources TVP5150AM1 HomepageCardBus / Digital Bus Interface Electrical Specifications DC Minimum Nominal MaximumPcmcia Interface Resources Pcmcia Website PCI SIG Website Device Jtag Debug InterfaceInstruction register bit length PSoC Debug Interface Connector Information Appendix a Peripheral I/O Connector InformationPeripheral I/O Connector Pinout Peripheral Connector Drawing FCI Appendix B CardBus Connector InformationCardBus Interface Schematic Pcicpar CardBus Connector PinoutPCICAD17 Fpga Pinout Appendix C Fpga PinoutCAD0 AA4 ETHERTX1 FLASHD11 RAMDQ5 Vdcfid Cpld Pinout Appendix D Cpld PinoutPSoC Pinout Appendix E PSoC PinoutStandard Part Number Listing Appendix F Standard Part Number ListingDevice Part Number Website Appendix G Errata Appendix H Fpga Performance Enhancements Revision History Legal Notices
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