Pico Communications E-15 manual PowerPC Processor, PPC405x3 Processor Introduction

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PowerPC™ Processor

PPC405x3 Processor Introduction:

FPGAs are renowned for their ability to process parallel logic, but they typically have a hard time emulating a high performance processor. To get the best of both worlds the Virtex-4™ features an embedded Power PC Processor. Since the processor shares the same die as the FPGA it seamlessly interfaces with the FPGA fabric.

A new feature of the Virtex-4 FPGA is the addition of an auxiliary processor interface. The APU is the highest speed interface between the PowerPC™ processor and the FPGA fabric. Up to four custom instructions may be implemented in the FPGA, which are accessible from the PowerPC™.

Board support packages are currently available for µC/OS and Linux. Board support source code is available open source under the GPL.

Pico E-15 Hardware Reference	www.picocomputing.com	Pico Computing
	(206) 283-2178	150 Nickerson Street. Suite 311
		Seattle, WA 98109

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Contents Release For Hardware Revision D Pico E-15Page Product Overview IO Connectivity Pico E-15 Quick Reference DatasheetStandard Part Numbers Standard Part NumberMilitary version is available which includes System Architecture Minimum Nominal Maximum Pico E-15 Electrical SpecificationField Programmable Gate Array PPC405x3 Processor Introduction PowerPC ProcessorCpld Resources Xilinx Cpld Website Cpld TurboLoaderFlash Memory DDR2 Sdram Memory RAMParameter Value EDK Value 133 MHz 333 MHz RAM Timing and Parameter InformationElectrical Specifications Minimum Nominal Maximum Temperature SensorSleep Controller Ethernet Resources Tri-Mode Ethernet InterfaceHI-Z Digital Peripheral InterfaceHigh Speed Analog to Digital Converters VDC Low pass filter range is customizable via special order High Speed Digital to Analog Converters Page Video Digitizer External Connections Composite Mode Video Digitizer External Connections Svideo ModeVideo Digitizer Video Digitizer Resources TVP5150AM1 HomepageElectrical Specifications DC Minimum Nominal Maximum CardBus / Digital Bus InterfacePcmcia Interface Resources Pcmcia Website PCI SIG Website Jtag Debug Interface DeviceInstruction register bit length PSoC Debug Interface Appendix a Peripheral I/O Connector Information Connector InformationPeripheral I/O Connector Pinout Peripheral Connector Drawing FCI Appendix B CardBus Connector InformationCardBus Interface Schematic Pcicpar CardBus Connector PinoutPCICAD17 Fpga Pinout Appendix C Fpga PinoutCAD0 AA4 ETHERTX1 FLASHD11 RAMDQ5 Vdcfid Cpld Pinout Appendix D Cpld PinoutPSoC Pinout Appendix E PSoC PinoutAppendix F Standard Part Number Listing Standard Part Number ListingDevice Part Number Website Appendix G Errata Appendix H Fpga Performance Enhancements Revision History Legal Notices