Pico Communications E-15 manual CAD0

Page 34

34

C\I\N\T\

F4

Interrupt Request

O

PCI33_3

Float

2mA

C\I\R\D\Y\

D4

Initiator Ready

I/O

PCI33_3

Float

2mA

C\P\E\R\R\

H3

Parity Error

I/O

PCI33_3

Float

2mA

C\R\E\Q\

A10

Access Request

O

PCI33_3

Float

2mA

C\R\S\T\

A8

Reset

I

PCI33_3

Float

 

C\S\E\R\R\

A9

System Error

I/O

PCI33_3

Float

2mA

C\S\T\O\P\

F3

Stop Request

I/O

PCI33_3

Float

2mA

C\T\R\D\Y\

D3

Target Ready

I/O

PCI33_3

Float

2mA

CAD0

AD15

Data / Address #0

I/O

PCI33_3

Float

2mA

CAD1

AE15

Data / Address #1

I/O

PCI33_3

Float

2mA

CAD2

AF15

Data / Address #2

I/O

PCI33_3

Float

2mA

CAD3

AF14

Data / Address #3

I/O

PCI33_3

Float

2mA

CAD4

AD14

Data / Address #4

I/O

PCI33_3

Float

2mA

CAD5

AC14

Data / Address #5

I/O

PCI33_3

Float

2mA

CAD6

AA13

Data / Address #6

I/O

PCI33_3

Float

2mA

CAD7

AB12

Data / Address #7

I/O

PCI33_3

Float

2mA

CAD8

AC13

Data / Address #8

I/O

PCI33_3

Float

2mA

CAD9

AD13

Data / Address #9

I/O

PCI33_3

Float

2mA

CAD10

AC12

Data / Address #10

I/O

PCI33_3

Float

2mA

CAD11

AA12

Data / Address #11

I/O

PCI33_3

Float

2mA

CAD12

AB14

Data / Address #12

I/O

PCI33_3

Float

2mA

CAD13

AA14

Data / Address #13

I/O

PCI33_3

Float

2mA

CAD14

M6

Data / Address #14

I/O

PCI33_3

Float

2mA

CAD15

M5

Data / Address #15

I/O

PCI33_3

Float

2mA

CAD16

K3

Data / Address #16

I/O

PCI33_3

Float

2mA

CAD17

C4

Data / Address #17

I/O

PCI33_3

Float

2mA

CAD18

C7

Data / Address #18

I/O

PCI33_3

Float

2mA

CAD19

B6

Data / Address #19

I/O

PCI33_3

Float

2mA

CAD20

A7

Data / Address #20

I/O

PCI33_3

Float

2mA

CAD21

B7

Data / Address #21

I/O

PCI33_3

Float

2mA

CAD22

B9

Data / Address #22

I/O

PCI33_3

Float

2mA

CAD23

B10

Data / Address #23

I/O

PCI33_3

Float

2mA

CAD24

B11

Data / Address #24

I/O

PCI33_3

Float

2mA

CAD25

A12

Data / Address #25

I/O

PCI33_3

Float

2mA

CAD26

B12

Data / Address #26

I/O

PCI33_3

Float

2mA

CAD27

A13

Data / Address #27

I/O

PCI33_3

Float

2mA

CAD28

C8

Data / Address #28

I/O

PCI33_3

Float

2mA

CAD29

C13

Data / Address #29

I/O

PCI33_3

Float

2mA

CAD30

E10

Data / Address #30

I/O

PCI33_3

Float

2mA

CAD31

D10

Data / Address #31

I/O

PCI33_3

Float

2mA

CAUDIO

E8

Audio

O

PCI33_3

Float

2mA

CCLK

E11

CardBus 33 MHz Clock

I

PCI33_3

Float

 

CCLKRUN

E13

Clock Request

O

PCI33_3

Float

2mA

CPAR

J4

Parity Even

I/O

PCI33_3

Float

2mA

CSTSCHG

D8

Status Change Interrupt

O

PCI33_3

Float

2mA

DAC_1_CLK_IN+

AC4

Differential Clock In +

O

DIFF HSTL II

Float

 

DAC_1_CLK_IN-

AC3

Differential Clock In -

O

DIFF HSTL II

Float

 

DAC_1_D0

W5

Data Out #0

O

LVTTL

Float

4mA

DAC_1_D1

W4

Data Out #1

O

LVTTL

Float

4mA

DAC_1_D2

Y3

Data Out #2

O

LVTTL

Float

4mA

Pico E-15 Hardware Reference

www.picocomputing.com

Pico Computing

 

(206) 283-2178

150 Nickerson Street. Suite 311

 

 

Seattle, WA 98109

Image 34
Contents Pico E-15 Release For Hardware Revision DPage Product Overview Pico E-15 Quick Reference Datasheet IO ConnectivityStandard Part Number Standard Part NumbersMilitary version is available which includes System Architecture Pico E-15 Electrical Specification Minimum Nominal MaximumField Programmable Gate Array PowerPC Processor PPC405x3 Processor IntroductionCpld TurboLoader Cpld Resources Xilinx Cpld WebsiteFlash Memory RAM DDR2 Sdram MemoryRAM Timing and Parameter Information Parameter Value EDK Value 133 MHz 333 MHzTemperature Sensor Electrical Specifications Minimum Nominal MaximumSleep Controller Tri-Mode Ethernet Interface Ethernet ResourcesDigital Peripheral Interface HI-ZHigh Speed Analog to Digital Converters VDC Low pass filter range is customizable via special order High Speed Digital to Analog Converters Page Video Digitizer Video Digitizer External Connections Svideo ModeVideo Digitizer External Connections Composite Mode Video Digitizer Resources TVP5150AM1 HomepageCardBus / Digital Bus Interface Electrical Specifications DC Minimum Nominal MaximumPcmcia Interface Resources Pcmcia Website PCI SIG Website Device Jtag Debug InterfaceInstruction register bit length PSoC Debug Interface Connector Information Appendix a Peripheral I/O Connector InformationPeripheral I/O Connector Pinout Peripheral Connector Drawing Appendix B CardBus Connector Information FCICardBus Interface Schematic CardBus Connector Pinout PcicparPCICAD17 Appendix C Fpga Pinout Fpga PinoutCAD0 AA4 ETHERTX1 FLASHD11 RAMDQ5 Vdcfid Appendix D Cpld Pinout Cpld PinoutAppendix E PSoC Pinout PSoC PinoutStandard Part Number Listing Appendix F Standard Part Number ListingDevice Part Number Website Appendix G Errata Appendix H Fpga Performance Enhancements Revision History Legal Notices