Pico Communications E-15 manual Appendix H Fpga Performance Enhancements

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Appendix H – FPGA Performance Enhancements

Overview:

Like most silicon devices, the FPGA on the Pico E-15 can be overclocked if proper cooling techniques are employed. Care must be taken to avoid thermal runaway.

Thermal Runaway:

As the die temperature of the FPGA increases, it draws more power. This extra power gets turned into heat. If thermal equilibrium is not reached with proper cooling, the FPGA will overheat. The E-15 is protected against catestropic overtemperature conditions via the integrated temperature sensor, although the limits should not routinely be pushed. The maximum FPGA core temperature is 150°C. Note that chips surrounding the FPGA can be damaged by temperatures above 70°C.

Heat Sink Placement:

The heat sink of the FPGA is internally connected via thermal grease to the case of the CardBus card on the bottom side (no markings). Placing a large heat sink on the outside of the case can allow higher performance.

Pico E-15 Hardware Reference

www.picocomputing.com

Pico Computing

 

(206) 283-2178

150 Nickerson Street. Suite 311

 

 

Seattle, WA 98109

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Contents Pico E-15 Release For Hardware Revision DPage Product Overview Pico E-15 Quick Reference Datasheet IO ConnectivityMilitary version is available which includes Standard Part NumbersStandard Part Number System Architecture Pico E-15 Electrical Specification Minimum Nominal MaximumField Programmable Gate Array PowerPC Processor PPC405x3 Processor IntroductionCpld TurboLoader Cpld Resources Xilinx Cpld WebsiteFlash Memory RAM DDR2 Sdram MemoryRAM Timing and Parameter Information Parameter Value EDK Value 133 MHz 333 MHzTemperature Sensor Electrical Specifications Minimum Nominal MaximumSleep Controller Tri-Mode Ethernet Interface Ethernet ResourcesDigital Peripheral Interface HI-ZHigh Speed Analog to Digital Converters VDC Low pass filter range is customizable via special order High Speed Digital to Analog Converters Page Video Digitizer External Connections Svideo Mode Video Digitizer External Connections Composite ModeVideo Digitizer Video Digitizer Resources TVP5150AM1 HomepagePcmcia Interface Resources Pcmcia Website PCI SIG Website Electrical Specifications DC Minimum Nominal MaximumCardBus / Digital Bus Interface Instruction register bit length Jtag Debug InterfaceDevice PSoC Debug Interface Peripheral I/O Connector Pinout Appendix a Peripheral I/O Connector InformationConnector Information Peripheral Connector Drawing Appendix B CardBus Connector Information FCICardBus Interface Schematic CardBus Connector Pinout PcicparPCICAD17 Appendix C Fpga Pinout Fpga PinoutCAD0 AA4 ETHERTX1 FLASHD11 RAMDQ5 Vdcfid Appendix D Cpld Pinout Cpld PinoutAppendix E PSoC Pinout PSoC PinoutDevice Part Number Website Appendix F Standard Part Number ListingStandard Part Number Listing Appendix G Errata Appendix H Fpga Performance Enhancements Revision History Legal Notices