SUPERSERVER
Note: "(B)" indicates black.
1-2 Serverboard Features
At the heart of the SuperServer
Chipset
The
The Intel 8870 chipset consists of the four primary components: the Scalable Node Controller (SNC), the Server I/O Hub (SIOH), the DDR Memory Hub (DMH), and the Scalability Port Switch (SPS). Complementary components include the I/O Hub Controller (Intel ICH4), the Firmware Hub (FWH), and the PCI Bus Bridge (P64H2).
The SNC is the main component in the processor/memory subsystem. It con- nects to four DDR memory hubs through four separate links to provide a peak memory bandwidth of 6.4 GB/s. Each DDR Memory Hub connects to two branch channels and supports up to four DDR SDRAM DIMMs per channel. The Scalability Port (SP) provides simultaneous,
The SIOH is the central component of the I/O subsystem and provides the connection between four Hub Interface 2.0 ports and two Scalability Ports. The the SIOH with four Hub Interfaces has a aggregate peak bandwidth of 4 GB/sec. The SIOH also offers a Hub Interface 1.5 connection to legacy I/O and firmware via the I/O Controller Hub (ICH4).
The DMH is a bridge for data transfers between the SNC and the two DDR memory channels. Each DMH has a maximum throughput of 1.6 GB/s and sup- ports up to eight single or double density registered DIMMs.
The SPS is not used in the