Cypress CY7C1381D, CY7C1383F, CY7C1381F manual Features, Selection Guide, MHz 100 MHz Unit

Page 1

CY7C1381D, CY7C1381F

CY7C1383D, CY7C1383F

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Features

Functional Description [1]

•Supports 133 MHz bus operations

•512K × 36 and 1M × 18 common IO

•3.3V core power supply (VDD)

•2.5V or 3.3V IO supply (VDDQ)

•Fast clock-to-output time

— 6.5 ns (133 MHz version)

•Provides high performance 2-1-1-1 access rate

•User selectable burst counter supporting Intel→ Pentium→ interleaved or linear burst sequences

•Separate processor and controller address strobes

•Synchronous self-timed write

•Asynchronous output enable

•CY7C1381D/CY7C1383D available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA package. CY7C1381F/CY7C1383F available in Pb-free and non Pb-free 119-ball BGA package

•IEEE 1149.1 JTAG-Compatible Boundary Scan

•ZZ sleep mode option

Selection Guide

The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a 3.3V, 512K x 36 and 1M x 18 synchronous flow through SRAMs, designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address pipelining chip enable (CE1), depth-expansion chip enables (CE2 and CE3 [2]), burst control inputs (ADSC, ADSP, and ADV), write enables (BWx, and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin.

The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F allows interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the processor address strobe (ADSP) or the cache controller address strobe (ADSC) inputs. Address advancement is controlled by the address advancement (ADV) input.

Addresses and chip enables are registered at rising edge of clock when address strobe processor (ADSP) or address strobe controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the advance pin (ADV).

The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F operates from a +3.3V core power supply while all outputs operate with a +2.5V or +3.3V supply. All inputs and outputs are JEDEC-standard and JESD8-5-compatible.

 

133 MHz

100 MHz

Unit

Maximum Access Time

6.5

8.5

ns

 

 

 

 

Maximum Operating Current

210

175

mA

 

 

 

 

Maximum CMOS Standby Current

70

70

mA

 

 

 

 

Notes:

1.For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.

2.CE3, CE2 are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable.

Cypress Semiconductor Corporation

•

198 Champion Court • San Jose, CA 95134-1709

•

408-943-2600

Document #: 38-05544 Rev. *F

 

Revised Feburary 07, 2007

[+] Feedback

Page 1 Page 2
Image 1
Page 1 Page 2
Contents Selection Guide Features133 MHz 100 MHz Unit Cypress Semiconductor CorporationCY7C1381D, CY7C1381F CY7C1381D 512K x Pin Configurations Pin Tqfp Pinout 3 Chip EnableCY7C1383D 1M x Pin Configurations Pin Configurations Ball Fbga Pinout3 Chip Enable Name Description Pin DefinitionsByte write select inputs, active LOW. Qualified with Functional Overview ZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDAddress = GNDCE1 CE2 CE3 Adsp Adsc ADV Write CLK Cycle Description UsedFunction CY7C1381D/CY7C1381F Truth Table for Read/Write 4DQPB, Dqpa DQPC, DqpaTAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Bypass RegisterTAP Timing TAP AC Switching Characteristics3V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Parameter Description Conditions MinScan Register Sizes Identification Register DefinitionsIdentification Codes Bit Size ×36 Bit Size ×18Bit # Ball ID Ball BGA Boundary Scan Order 14A11 Maximum Ratings Electrical CharacteristicsOperating Range Ambient RangeThermal Resistance CapacitanceAC Test Loads and Waveforms 133 MHz 100 MHz Parameter Description Unit Min Switching CharacteristicsRead Cycle Timing Timing DiagramsAddress BWE Write Cycle Timing 26ADV Read/Write Cycle Timing 26, 28ZZ Mode Timing 30 Ordering Information Pin Thin Plastic Quad Flat pack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change

CY7C1381D, CY7C1381F, CY7C1383D, CY7C1383F specifications

The Cypress CY7C1383F, CY7C1383D, CY7C1381F, and CY7C1381D are high-performance static random-access memory (SRAM) devices designed for a variety of applications requiring fast data storage and retrieval. These memory chips are part of the Cypress SRAM family, known for their low power consumption, high speed, and data integrity, making them suitable for use in telecommunications, networking, and industrial applications.

One of the standout features of the CY7C1383F and CY7C1383D models is their high density, offering 256K bits of memory. This provides ample space for storing critical data while maintaining excellent performance. The CY7C1381F and CY7C1381D variants, having a smaller capacity of 128K bits, are ideal for applications where space and power savings are paramount. All four devices are organized as 32K x 8 bits, promoting ease of integration into various designs.

These SRAM devices utilize advanced CMOS technology, which not only enhances their speed but also reduces power consumption. The fast access times, reaching as low as 10 nanoseconds for the CY7C1383F and CY7C1381F, enable high-speed data processing, making these memories suitable for cache applications and high-speed buffering. Overall, their performance characteristics ensure data can be accessed quickly and efficiently.

The CY7C1383F and CY7C1383D models come with an extended temperature range, ensuring consistent performance even in harsh environments. This reliability is critical for industrial applications where fluctuating temperatures can affect device functionality. Moreover, the CY7C1381F and CY7C1381D share this advantage, making all four components suitable for different operating conditions.

Built-in features such as byte-wide write enable and chip enable signals significantly ease the control of data access and manipulation. Additionally, the asynchronous nature of these SRAM devices allows for simple interfacing with various microcontrollers and processors, facilitating integration into existing systems with minimal design modifications.

In summary, the Cypress CY7C1383F, CY7C1383D, CY7C1381F, and CY7C1381D SRAM devices deliver high-performance data storage solutions, characterized by low power consumption, fast access times, and reliability in diverse operating conditions. Their versatility makes them an excellent choice for engineers seeking robust memory solutions in their designs.
Top Page Image Contents