Cypress CY7C1381D, CY7C1383F, CY7C1381F, CY7C1383D TAP Timing, TAP AC Switching Characteristics

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CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F

(Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the Shift-DR state. During Update-DR, the value loaded into that shift-register cell will latch into the preload register. When the EXTEST instruction is entered, this bit will

directly control the output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered up, and also when the TAP controller is in the Test-Logic-Reset state.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

TAP Timing

1

2

Test Clock

 

(TCK)

tTH

 

tTMSS

tTMSH

Test Mode Select

 

(TMS)

 

tTDIS

tTDIH

Test Data-In

 

(TDI)

 

Test Data-Out

 

(TDO)

 

3

tTL tCYC

4

5

6

 

 

 

tTDOV

tTDOX

DON’T CARE

UNDEFINED

TAP AC Switching Characteristics

Over the Operating Range [10, 11]

Parameter

Description

Min

Max

Unit

Clock

 

 

 

 

 

 

 

 

 

tTCYC

TCK Clock Cycle Time

50

 

ns

tTF

TCK Clock Frequency

 

20

MHz

tTH

TCK Clock HIGH time

20

 

ns

tTL

TCK Clock LOW time

20

 

ns

Output Times

 

 

 

 

tTDOV

TCK Clock LOW to TDO Valid

 

10

ns

tTDOX

TCK Clock LOW to TDO Invalid

0

 

ns

Setup Times

 

 

 

 

tTMSS

TMS Setup to TCK Clock Rise

5

 

ns

tTDIS

TDI Setup to TCK Clock Rise

5

 

ns

tCS

Capture Setup to TCK Rise

5

 

ns

Hold Times

 

 

 

 

 

 

 

 

 

tTMSH

TMS Hold after TCK Clock Rise

5

 

ns

tTDIH

TDI Hold after Clock Rise

5

 

ns

tCH

Capture Hold after Clock Rise

5

 

ns

Notes:

10.tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

11.Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.

Document #: 38-05544 Rev. *F

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Contents Selection Guide Features133 MHz 100 MHz Unit Cypress Semiconductor CorporationCY7C1381D, CY7C1381F CY7C1381D 512K x Pin Configurations Pin Tqfp Pinout 3 Chip EnableCY7C1383D 1M x Pin Configurations Pin Configurations Ball Fbga Pinout3 Chip Enable Name Description Pin DefinitionsByte write select inputs, active LOW. Qualified with Functional Overview ZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDAddress = GNDCE1 CE2 CE3 Adsp Adsc ADV Write CLK Cycle Description UsedFunction CY7C1381D/CY7C1381F Truth Table for Read/Write 4DQPB, Dqpa DQPC, DqpaTAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Bypass RegisterTAP Timing TAP AC Switching Characteristics3V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Parameter Description Conditions MinScan Register Sizes Identification Register DefinitionsIdentification Codes Bit Size ×36 Bit Size ×18Bit # Ball ID Ball BGA Boundary Scan Order 14A11 Maximum Ratings Electrical CharacteristicsOperating Range Ambient RangeThermal Resistance CapacitanceAC Test Loads and Waveforms 133 MHz 100 MHz Parameter Description Unit Min Switching CharacteristicsRead Cycle Timing Timing DiagramsAddress BWE Write Cycle Timing 26ADV Read/Write Cycle Timing 26, 28ZZ Mode Timing 30 Ordering Information Pin Thin Plastic Quad Flat pack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change

CY7C1381D, CY7C1381F, CY7C1383D, CY7C1383F specifications

The Cypress CY7C1383F, CY7C1383D, CY7C1381F, and CY7C1381D are high-performance static random-access memory (SRAM) devices designed for a variety of applications requiring fast data storage and retrieval. These memory chips are part of the Cypress SRAM family, known for their low power consumption, high speed, and data integrity, making them suitable for use in telecommunications, networking, and industrial applications.

One of the standout features of the CY7C1383F and CY7C1383D models is their high density, offering 256K bits of memory. This provides ample space for storing critical data while maintaining excellent performance. The CY7C1381F and CY7C1381D variants, having a smaller capacity of 128K bits, are ideal for applications where space and power savings are paramount. All four devices are organized as 32K x 8 bits, promoting ease of integration into various designs.

These SRAM devices utilize advanced CMOS technology, which not only enhances their speed but also reduces power consumption. The fast access times, reaching as low as 10 nanoseconds for the CY7C1383F and CY7C1381F, enable high-speed data processing, making these memories suitable for cache applications and high-speed buffering. Overall, their performance characteristics ensure data can be accessed quickly and efficiently.

The CY7C1383F and CY7C1383D models come with an extended temperature range, ensuring consistent performance even in harsh environments. This reliability is critical for industrial applications where fluctuating temperatures can affect device functionality. Moreover, the CY7C1381F and CY7C1381D share this advantage, making all four components suitable for different operating conditions.

Built-in features such as byte-wide write enable and chip enable signals significantly ease the control of data access and manipulation. Additionally, the asynchronous nature of these SRAM devices allows for simple interfacing with various microcontrollers and processors, facilitating integration into existing systems with minimal design modifications.

In summary, the Cypress CY7C1383F, CY7C1383D, CY7C1381F, and CY7C1381D SRAM devices deliver high-performance data storage solutions, characterized by low power consumption, fast access times, and reliability in diverse operating conditions. Their versatility makes them an excellent choice for engineers seeking robust memory solutions in their designs.
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