Cypress CY7C1383D, CY7C1383F Pin Configurations Pin Tqfp Pinout 3 Chip Enable, CY7C1381D 512K x

Page 3

CY7C1381D, CY7C1381F

CY7C1383D, CY7C1383F

Pin Configurations

100-pin TQFP Pinout (3 Chip Enable)

DQPC

DQC

DQC

VDDQ

VSSQ

DQC

DQC

DQC

DQC

VSSQ

VDDQ

DQC

DQC VSS/DNU VDD NC VSS

DQD DQD

VDDQ

VSSQ

DQD

DQD

DQD

DQD

VSSQ

VDDQ

DQD

DQD DQPD

	A A CE						CE		BWD BWC BWB BWA CE V V CLK GW																		BWE OE			ADSC			ADSP	ADV A A
1							2										3 DD SS
																	3 DD SS



100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1																												80
2																												79
3																												78
4																												77
5																												76
6																												75
7																												74
8																												73
9																												72
10																												71
11																												70
12																												69
13																												68
14																												67
15														CY7C1381D														66
16														CY7C1381D														65
17															(512K x 36)													64
18																												63
19																												62
20																												61
21																												60
22																												59
23																												58
24																												57
25																												56
26																												55
27																												54
28																												53
29																												52
30																												51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

DQPB	NC
DQB	NC
DQB	NC
VDDQ	VDDQ
VSSQ	VSSQ
DQB	NC
DQB	NC
DQB	DQB
DQB	DQB
VSSQ	VSSQ
VDDQ	VDDQ
DQB	DQB
DQB	DQB
VSS	VSS/DNU
NC	VDD
VDD	NC
ZZ	VSS
DQA	DQB
DQA	DQB
VDDQ	VDDQ
VSSQ	VSSQ
DQA	DQB
DQA	DQB
DQA	DQPB
DQA	NC
VSSQ	VSSQ
VDDQ	VDDQ
DQA	NC
DQA	NC
DQPA	NC

	A A CE CE								NC NC BWB						BWA CE V V CLK GW													BWE OE				ADSC			ADSP	ADV A A
1 2																		3 DD SS
																		3 DD SS



100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1																														80
2																														79
3																														78
4																														77
5																														76
6																														75
7																														74
8																														73
9																														72
10																														71
11																														70
12																														69
13																														68
14															CY7C1383D															67
15															CY7C1383D															66
16																(1M x 18)														65
17																(1M x 18)														64
17																														64
18																														63
19																														62
20																														61
21																														60
22																														59
23																														58
24																														57
25																														56
26																														55
27																														54
28																														53
29																														52
30																														51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

A

NC

NC

VDDQ VSSQ

NC DQPA DQA DQA

VSSQ

VDDQ

DQA

DQA

VSS

NC

VDD

ZZ

DQA DQA

VDDQ

VSSQ DQA DQA NC NC

VSSQ VDDQ

NC

NC

NC

MODE A A A A A	A	NC NC V V A A A A A A A A A
1	0	SS DD

MODE A A A A A	A	NC NC V V A A A A A A A A A
1	0	SS DD

Document #: 38-05544 Rev. *F

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Contents Cypress Semiconductor Corporation FeaturesSelection Guide 133 MHz 100 MHz UnitCY7C1381D, CY7C1381F Pin Configurations Pin Tqfp Pinout 3 Chip Enable CY7C1381D 512K xCY7C1383D 1M x Pin Configurations Pin Configurations Ball Fbga Pinout3 Chip Enable Pin Definitions Name DescriptionByte write select inputs, active LOW. Qualified with Functional Overview = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics AddressCE1 CE2 CE3 Adsp Adsc ADV Write CLK Cycle Description UsedDQPC, Dqpa Truth Table for Read/Write 4Function CY7C1381D/CY7C1381F DQPB, DqpaTAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Bypass RegisterTAP Timing TAP AC Switching CharacteristicsParameter Description Conditions Min TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions 5V TAP AC Test ConditionsBit Size ×36 Bit Size ×18 Identification Register DefinitionsScan Register Sizes Identification CodesBit # Ball ID Ball BGA Boundary Scan Order 14A11 Ambient Range Electrical CharacteristicsMaximum Ratings Operating RangeCapacitance Thermal ResistanceAC Test Loads and Waveforms 133 MHz 100 MHz Parameter Description Unit Min Switching CharacteristicsRead Cycle Timing Timing DiagramsAddress BWE Write Cycle Timing 26ADV Read/Write Cycle Timing 26, 28ZZ Mode Timing 30 Ordering Information Pin Thin Plastic Quad Flat pack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change

CY7C1381D, CY7C1381F, CY7C1383D, CY7C1383F specifications

The Cypress CY7C1383F, CY7C1383D, CY7C1381F, and CY7C1381D are high-performance static random-access memory (SRAM) devices designed for a variety of applications requiring fast data storage and retrieval. These memory chips are part of the Cypress SRAM family, known for their low power consumption, high speed, and data integrity, making them suitable for use in telecommunications, networking, and industrial applications.

One of the standout features of the CY7C1383F and CY7C1383D models is their high density, offering 256K bits of memory. This provides ample space for storing critical data while maintaining excellent performance. The CY7C1381F and CY7C1381D variants, having a smaller capacity of 128K bits, are ideal for applications where space and power savings are paramount. All four devices are organized as 32K x 8 bits, promoting ease of integration into various designs.

These SRAM devices utilize advanced CMOS technology, which not only enhances their speed but also reduces power consumption. The fast access times, reaching as low as 10 nanoseconds for the CY7C1383F and CY7C1381F, enable high-speed data processing, making these memories suitable for cache applications and high-speed buffering. Overall, their performance characteristics ensure data can be accessed quickly and efficiently.

The CY7C1383F and CY7C1383D models come with an extended temperature range, ensuring consistent performance even in harsh environments. This reliability is critical for industrial applications where fluctuating temperatures can affect device functionality. Moreover, the CY7C1381F and CY7C1381D share this advantage, making all four components suitable for different operating conditions.

Built-in features such as byte-wide write enable and chip enable signals significantly ease the control of data access and manipulation. Additionally, the asynchronous nature of these SRAM devices allows for simple interfacing with various microcontrollers and processors, facilitating integration into existing systems with minimal design modifications.

In summary, the Cypress CY7C1383F, CY7C1383D, CY7C1381F, and CY7C1381D SRAM devices deliver high-performance data storage solutions, characterized by low power consumption, fast access times, and reliability in diverse operating conditions. Their versatility makes them an excellent choice for engineers seeking robust memory solutions in their designs.