Cypress CY7C1383F, CY7C1381D manual Interleaved Burst Address Table Mode = Floating or VDD, = Gnd

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CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F

deasserted and the IOs must be tri-stated prior to the presen- tation of data to DQs. As a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of OE.

Single Write Accesses Initiated by ADSC

This write access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 [2] are all

asserted active, (2) ADSC is asserted LOW, (3) ADSP is deasserted HIGH, and (4) the write input signals (GW, BWE, and BWX) indicate a write access. ADSC is ignored if ADSP is active LOW.

The addresses presented are loaded into the address register and the burst counter, the control logic, or both, and delivered to the memory core The information presented to DQ[A:D] will be written into the specified address location. Byte writes are allowed. All IOs are tri-stated when a write is detected, even a byte write. Since this is a common IO device, the asynchronous OE input signal must be deasserted and the IOs must be tri-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of OE.

Burst Sequences

The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F provides an on-chip two-bit wraparound burst counter inside the SRAM. The burst counter is fed by A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE will select a linear burst sequence. A HIGH on MODE will select an interleaved burst order. Leaving MODE unconnected will cause the device to default to a interleaved burst sequence.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation sleep mode. Two clock cycles are required to enter into or exit from this sleep mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the sleep mode. CE1, CE2, CE3 [2], ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW.

Interleaved Burst Address Table (MODE = Floating or VDD)

First

Second

Third

Fourth

Address

Address

Address

Address

A1: A0

A1: A0

A1: A0

A1: A0

00

01

10

11

 

 

 

 

01

00

11

10

 

 

 

 

10

11

00

01

 

 

 

 

11

10

01

00

 

 

 

 

Linear Burst

Address

Table (MODE

= GND)

First

Second

Third

Fourth

Address

Address

Address

Address

A1: A0

A1: A0

A1: A0

A1: A0

00

01

10

11

 

 

 

 

01

10

11

00

 

 

 

 

10

11

00

01

 

 

 

 

11

00

01

10

 

 

 

 

ZZ Mode Electrical Characteristics

Parameter

Description

Test Conditions

Min

Max

Unit

IDDZZ

Sleep mode standby current

ZZ > VDD – 0.2V

 

80

mA

tZZS

Device operation to ZZ

ZZ > VDD – 0.2V

 

2tCYC

ns

tZZREC

ZZ recovery time

ZZ < 0.2V

2tCYC

 

ns

tZZI

ZZ active to sleep current

This parameter is sampled

 

2tCYC

ns

tRZZI

ZZ inactive to exit sleep current

This parameter is sampled

0

 

ns

Document #: 38-05544 Rev. *F

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Contents Features Selection Guide133 MHz 100 MHz Unit Cypress Semiconductor CorporationCY7C1381D, CY7C1381F CY7C1383D 1M x Pin Configurations Pin Tqfp Pinout 3 Chip EnableCY7C1381D 512K x Pin Configurations Pin Configurations Ball Fbga Pinout3 Chip Enable Byte write select inputs, active LOW. Qualified with Pin DefinitionsName Description Functional Overview Interleaved Burst Address Table Mode = Floating or VDD ZZ Mode Electrical CharacteristicsAddress = GNDCycle Description Used CE1 CE2 CE3 Adsp Adsc ADV Write CLKTruth Table for Read/Write 4 Function CY7C1381D/CY7C1381FDQPB, Dqpa DQPC, DqpaIeee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Controller Block Diagram Bypass Register TAP Instruction SetTAP AC Switching Characteristics TAP TimingTAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test Conditions5V TAP AC Test Conditions Parameter Description Conditions MinIdentification Register Definitions Scan Register SizesIdentification Codes Bit Size ×36 Bit Size ×18Ball BGA Boundary Scan Order 14 Bit # Ball IDA11 Electrical Characteristics Maximum RatingsOperating Range Ambient RangeAC Test Loads and Waveforms CapacitanceThermal Resistance Switching Characteristics 133 MHz 100 MHz Parameter Description Unit MinTiming Diagrams Read Cycle TimingWrite Cycle Timing 26 Address BWERead/Write Cycle Timing 26, 28 ADVZZ Mode Timing 30 Ordering Information Package Diagrams Pin Thin Plastic Quad Flat pack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History

CY7C1381D, CY7C1381F, CY7C1383D, CY7C1383F specifications

The Cypress CY7C1383F, CY7C1383D, CY7C1381F, and CY7C1381D are high-performance static random-access memory (SRAM) devices designed for a variety of applications requiring fast data storage and retrieval. These memory chips are part of the Cypress SRAM family, known for their low power consumption, high speed, and data integrity, making them suitable for use in telecommunications, networking, and industrial applications.

One of the standout features of the CY7C1383F and CY7C1383D models is their high density, offering 256K bits of memory. This provides ample space for storing critical data while maintaining excellent performance. The CY7C1381F and CY7C1381D variants, having a smaller capacity of 128K bits, are ideal for applications where space and power savings are paramount. All four devices are organized as 32K x 8 bits, promoting ease of integration into various designs.

These SRAM devices utilize advanced CMOS technology, which not only enhances their speed but also reduces power consumption. The fast access times, reaching as low as 10 nanoseconds for the CY7C1383F and CY7C1381F, enable high-speed data processing, making these memories suitable for cache applications and high-speed buffering. Overall, their performance characteristics ensure data can be accessed quickly and efficiently.

The CY7C1383F and CY7C1383D models come with an extended temperature range, ensuring consistent performance even in harsh environments. This reliability is critical for industrial applications where fluctuating temperatures can affect device functionality. Moreover, the CY7C1381F and CY7C1381D share this advantage, making all four components suitable for different operating conditions.

Built-in features such as byte-wide write enable and chip enable signals significantly ease the control of data access and manipulation. Additionally, the asynchronous nature of these SRAM devices allows for simple interfacing with various microcontrollers and processors, facilitating integration into existing systems with minimal design modifications.

In summary, the Cypress CY7C1383F, CY7C1383D, CY7C1381F, and CY7C1381D SRAM devices deliver high-performance data storage solutions, characterized by low power consumption, fast access times, and reliability in diverse operating conditions. Their versatility makes them an excellent choice for engineers seeking robust memory solutions in their designs.
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