Cypress CY7C1383F manual Switching Characteristics, MHz 100 MHz Parameter Description Unit Min

Page 20

CY7C1381D, CY7C1381F

CY7C1383D, CY7C1383F

Switching Characteristics

Over the Operating Range [20, 21]

 

 

 

 

 

 

 

 

 

 

 

 

 

133 MHz

100 MHz

 

Parameter

 

 

 

 

 

 

 

 

 

 

 

Description

 

 

 

 

Unit

 

 

 

 

 

 

 

 

 

 

 

Min

Max

Min

Max

 

 

 

 

 

 

 

 

tPOWER

 

VDD(Typical) to the first Access [22]

1

 

1

 

ms

Clock

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCYC

 

Clock Cycle Time

7.5

 

10

 

ns

tCH

 

Clock HIGH

2.1

 

2.5

 

ns

tCL

 

Clock LOW

2.1

 

2.5

 

ns

Output Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCDV

 

Data Output Valid After CLK Rise

 

6.5

 

8.5

ns

tDOH

 

Data Output Hold After CLK Rise

2.0

 

2.0

 

ns

tCLZ

 

Clock to Low-Z [23, 24, 25]

2.0

 

2.0

 

ns

tCHZ

 

Clock to High-Z [23, 24, 25]

0

4.0

0

5.0

ns

tOEV

 

 

 

LOW to Output Valid

 

3.2

 

3.8

ns

OE

 

 

tOELZ

 

 

 

LOW to Output Low-Z [23, 24, 25]

0

 

0

 

ns

OE

 

 

tOEHZ

 

 

 

HIGH to Output High-Z [23, 24, 25]

 

4.0

 

5.0

ns

OE

 

 

Setup Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tAS

 

Address Setup Before CLK Rise

1.5

 

1.5

 

ns

tADS

 

 

 

 

 

 

 

 

 

 

Setup Before CLK Rise

1.5

 

1.5

 

ns

ADSP,

ADSC

 

 

tADVS

 

 

 

 

 

Setup Before CLK Rise

1.5

 

1.5

 

ns

ADV

 

 

tWES

 

 

 

 

 

 

 

 

 

 

[A:D] Setup Before CLK Rise

1.5

 

1.5

 

ns

GW,

BWE,

BW

 

 

tDS

 

Data Input Setup Before CLK Rise

1.5

 

1.5

 

ns

tCES

 

Chip Enable Setup

1.5

 

1.5

 

ns

Hold Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tAH

 

Address Hold After CLK Rise

0.5

 

0.5

 

ns

tADH

 

 

 

 

 

 

 

 

 

 

Hold After CLK Rise

0.5

 

0.5

 

ns

ADSP,

ADSC

 

 

tWEH

 

 

 

 

 

 

 

 

 

 

[A:D] Hold After CLK Rise

0.5

 

0.5

 

ns

GW,

BWE,

BW

 

 

tADVH

 

 

 

 

Hold After CLK Rise

0.5

 

0.5

 

ns

ADV

 

 

tDH

 

Data Input Hold After CLK Rise

0.5

 

0.5

 

ns

tCEH

 

Chip Enable Hold After CLK Rise

0.5

 

0.5

 

ns

Notes:

20.Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.

21.Test conditions shown in (a) of AC Test Loads unless otherwise noted.

22.This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation can be initiated.

23.tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads and Waveforms on page 19. Transition is measured ± 200 mV from steady-state voltage.

24.At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system condition.

25.This parameter is sampled and not 100% tested.

Document #: 38-05544 Rev. *F

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Contents Features Selection Guide133 MHz 100 MHz Unit Cypress Semiconductor CorporationCY7C1381D, CY7C1381F CY7C1383D 1M x Pin Configurations Pin Tqfp Pinout 3 Chip EnableCY7C1381D 512K x Pin Configurations Pin Configurations Ball Fbga Pinout3 Chip Enable Byte write select inputs, active LOW. Qualified with Pin DefinitionsName Description Functional Overview Interleaved Burst Address Table Mode = Floating or VDD ZZ Mode Electrical CharacteristicsAddress = GNDCycle Description Used CE1 CE2 CE3 Adsp Adsc ADV Write CLKTruth Table for Read/Write 4 Function CY7C1381D/CY7C1381FDQPB, Dqpa DQPC, DqpaIeee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Controller Block Diagram Bypass Register TAP Instruction SetTAP AC Switching Characteristics TAP TimingTAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test Conditions5V TAP AC Test Conditions Parameter Description Conditions MinIdentification Register Definitions Scan Register SizesIdentification Codes Bit Size ×36 Bit Size ×18Ball BGA Boundary Scan Order 14 Bit # Ball IDA11 Electrical Characteristics Maximum RatingsOperating Range Ambient RangeAC Test Loads and Waveforms CapacitanceThermal Resistance Switching Characteristics 133 MHz 100 MHz Parameter Description Unit MinTiming Diagrams Read Cycle TimingWrite Cycle Timing 26 Address BWERead/Write Cycle Timing 26, 28 ADVZZ Mode Timing 30 Ordering Information Package Diagrams Pin Thin Plastic Quad Flat pack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History

CY7C1381D, CY7C1381F, CY7C1383D, CY7C1383F specifications

The Cypress CY7C1383F, CY7C1383D, CY7C1381F, and CY7C1381D are high-performance static random-access memory (SRAM) devices designed for a variety of applications requiring fast data storage and retrieval. These memory chips are part of the Cypress SRAM family, known for their low power consumption, high speed, and data integrity, making them suitable for use in telecommunications, networking, and industrial applications.

One of the standout features of the CY7C1383F and CY7C1383D models is their high density, offering 256K bits of memory. This provides ample space for storing critical data while maintaining excellent performance. The CY7C1381F and CY7C1381D variants, having a smaller capacity of 128K bits, are ideal for applications where space and power savings are paramount. All four devices are organized as 32K x 8 bits, promoting ease of integration into various designs.

These SRAM devices utilize advanced CMOS technology, which not only enhances their speed but also reduces power consumption. The fast access times, reaching as low as 10 nanoseconds for the CY7C1383F and CY7C1381F, enable high-speed data processing, making these memories suitable for cache applications and high-speed buffering. Overall, their performance characteristics ensure data can be accessed quickly and efficiently.

The CY7C1383F and CY7C1383D models come with an extended temperature range, ensuring consistent performance even in harsh environments. This reliability is critical for industrial applications where fluctuating temperatures can affect device functionality. Moreover, the CY7C1381F and CY7C1381D share this advantage, making all four components suitable for different operating conditions.

Built-in features such as byte-wide write enable and chip enable signals significantly ease the control of data access and manipulation. Additionally, the asynchronous nature of these SRAM devices allows for simple interfacing with various microcontrollers and processors, facilitating integration into existing systems with minimal design modifications.

In summary, the Cypress CY7C1383F, CY7C1383D, CY7C1381F, and CY7C1381D SRAM devices deliver high-performance data storage solutions, characterized by low power consumption, fast access times, and reliability in diverse operating conditions. Their versatility makes them an excellent choice for engineers seeking robust memory solutions in their designs.
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