Cypress CY7C1381D, CY7C1383F manual Cycle Description Used, CE1 CE2 CE3 Adsp Adsc ADV Write CLK

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CY7C1381D, CY7C1381F

CY7C1383D, CY7C1383F

Truth Table [4, 5, 6, 7, 8]

 

ADDRESS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cycle Description

Used

 

CE1

CE2

CE3

ZZ

ADSP

 

ADSC

 

ADV

 

 

WRITE

 

OE

 

CLK

DQ

Deselected Cycle, Power

None

 

H

X

 

X

 

L

 

X

 

L

 

X

 

 

X

 

X

 

L-H

Tri-State

Down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselected Cycle, Power

None

 

L

L

 

X

 

L

 

L

 

X

 

X

 

 

X

 

X

 

L-H

Tri-State

Down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselected Cycle, Power

None

 

L

X

 

H

 

L

 

L

 

X

 

X

 

 

X

 

X

 

L-H

Tri-State

Down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselected Cycle, Power

None

 

L

L

 

X

 

L

 

H

 

L

 

X

 

 

X

 

X

 

L-H

Tri-State

Down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselected Cycle, Power

None

 

X

X

 

X

 

L

 

H

 

L

 

X

 

 

X

 

X

 

L-H

Tri-State

Down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Sleep Mode, Power Down

None

 

X

X

 

X

 

H

 

X

 

X

 

X

 

 

X

 

X

 

X

Tri-State

Read Cycle, Begin Burst

External

 

L

H

 

L

 

L

 

L

 

X

 

X

 

 

X

 

L

 

L-H

Q

Read Cycle, Begin Burst

External

 

L

H

 

L

 

L

 

L

 

X

 

X

 

 

X

 

H

 

L-H

Tri-State

Write Cycle, Begin Burst

External

 

L

H

 

L

 

L

 

H

 

L

 

X

 

 

L

 

X

 

L-H

D

Read Cycle, Begin Burst

External

 

L

H

 

L

 

L

 

H

 

L

 

X

 

 

H

 

L

 

L-H

Q

Read Cycle, Begin Burst

External

 

L

H

 

L

 

L

 

H

 

L

 

X

 

 

H

 

H

 

L-H

Tri-State

Read Cycle, Continue Burst

Next

 

X

X

 

X

 

L

 

H

 

H

 

L

 

 

H

 

L

 

L-H

Q

Read Cycle, Continue Burst

Next

 

X

X

 

X

 

L

 

H

 

H

 

L

 

 

H

 

H

 

L-H

Tri-State

Read Cycle, Continue Burst

Next

 

H

X

 

X

 

L

 

X

 

H

 

L

 

 

H

 

L

 

L-H

Q

Read Cycle, Continue Burst

Next

 

H

X

 

X

 

L

 

X

 

H

 

L

 

 

H

 

H

 

L-H

Tri-State

Write Cycle, Continue Burst

Next

 

X

X

 

X

 

L

 

H

 

H

 

L

 

 

L

 

X

 

L-H

D

Write Cycle, Continue Burst

Next

 

H

X

 

X

 

L

 

X

 

H

 

L

 

 

L

 

X

 

L-H

D

Read Cycle, Suspend Burst

Current

 

X

X

 

X

 

L

 

H

 

H

 

H

 

 

H

 

L

 

L-H

Q

Read Cycle, Suspend Burst

Current

 

X

X

 

X

 

L

 

H

 

H

 

H

 

 

H

 

H

 

L-H

Tri-State

Read Cycle, Suspend Burst

Current

 

H

X

 

X

 

L

 

X

 

H

 

H

 

 

H

 

L

 

L-H

Q

Read Cycle, Suspend Burst

Current

 

H

X

 

X

 

L

 

X

 

H

 

H

 

 

H

 

H

 

L-H

Tri-State

Write Cycle, Suspend Burst

Current

 

X

X

 

X

 

L

 

H

 

H

 

H

 

 

L

 

X

 

L-H

D

Write Cycle, Suspend Burst

Current

 

H

X

 

X

 

L

 

X

 

H

 

H

 

 

L

 

X

 

L-H

D

Notes:

4.X=Don't Care, H = Logic HIGH, L = Logic LOW.

5.WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.

6.The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

7.The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the write cycle.

8.OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).

Document #: 38-05544 Rev. *F

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Contents Selection Guide Features133 MHz 100 MHz Unit Cypress Semiconductor CorporationCY7C1381D, CY7C1381F Pin Configurations Pin Tqfp Pinout 3 Chip Enable CY7C1381D 512K xCY7C1383D 1M x Pin Configurations Pin Configurations Ball Fbga Pinout3 Chip Enable Pin Definitions Name DescriptionByte write select inputs, active LOW. Qualified with Functional Overview ZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDAddress = GNDCE1 CE2 CE3 Adsp Adsc ADV Write CLK Cycle Description UsedFunction CY7C1381D/CY7C1381F Truth Table for Read/Write 4DQPB, Dqpa DQPC, DqpaTAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Bypass RegisterTAP Timing TAP AC Switching Characteristics3V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Parameter Description Conditions MinScan Register Sizes Identification Register DefinitionsIdentification Codes Bit Size ×36 Bit Size ×18Bit # Ball ID Ball BGA Boundary Scan Order 14A11 Maximum Ratings Electrical CharacteristicsOperating Range Ambient RangeCapacitance Thermal ResistanceAC Test Loads and Waveforms 133 MHz 100 MHz Parameter Description Unit Min Switching CharacteristicsRead Cycle Timing Timing DiagramsAddress BWE Write Cycle Timing 26ADV Read/Write Cycle Timing 26, 28ZZ Mode Timing 30 Ordering Information Pin Thin Plastic Quad Flat pack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change

CY7C1381D, CY7C1381F, CY7C1383D, CY7C1383F specifications

The Cypress CY7C1383F, CY7C1383D, CY7C1381F, and CY7C1381D are high-performance static random-access memory (SRAM) devices designed for a variety of applications requiring fast data storage and retrieval. These memory chips are part of the Cypress SRAM family, known for their low power consumption, high speed, and data integrity, making them suitable for use in telecommunications, networking, and industrial applications.

One of the standout features of the CY7C1383F and CY7C1383D models is their high density, offering 256K bits of memory. This provides ample space for storing critical data while maintaining excellent performance. The CY7C1381F and CY7C1381D variants, having a smaller capacity of 128K bits, are ideal for applications where space and power savings are paramount. All four devices are organized as 32K x 8 bits, promoting ease of integration into various designs.

These SRAM devices utilize advanced CMOS technology, which not only enhances their speed but also reduces power consumption. The fast access times, reaching as low as 10 nanoseconds for the CY7C1383F and CY7C1381F, enable high-speed data processing, making these memories suitable for cache applications and high-speed buffering. Overall, their performance characteristics ensure data can be accessed quickly and efficiently.

The CY7C1383F and CY7C1383D models come with an extended temperature range, ensuring consistent performance even in harsh environments. This reliability is critical for industrial applications where fluctuating temperatures can affect device functionality. Moreover, the CY7C1381F and CY7C1381D share this advantage, making all four components suitable for different operating conditions.

Built-in features such as byte-wide write enable and chip enable signals significantly ease the control of data access and manipulation. Additionally, the asynchronous nature of these SRAM devices allows for simple interfacing with various microcontrollers and processors, facilitating integration into existing systems with minimal design modifications.

In summary, the Cypress CY7C1383F, CY7C1383D, CY7C1381F, and CY7C1381D SRAM devices deliver high-performance data storage solutions, characterized by low power consumption, fast access times, and reliability in diverse operating conditions. Their versatility makes them an excellent choice for engineers seeking robust memory solutions in their designs.