Cypress CY7C1383D, CY7C1383F, CY7C1381D, CY7C1381F manual Functional Overview

Page 7

 

 

 

 

CY7C1381D, CY7C1381F

 

 

 

 

CY7C1383D, CY7C1383F

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Definitions (continued)

 

 

 

 

Name

IO

Description

 

 

 

MODE

Input-Static

Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD

 

 

 

 

or left floating selects interleaved burst sequence. This is a strap pin and must remain static

 

 

 

 

during device operation. Mode pin has an internal pull up.

 

 

 

VDD

Power Supply

Power supply inputs to the core of the device.

VDDQ

IO Power Supply

Power supply for the IO circuitry.

VSS

Ground

Ground for the core of the device.

VSSQ

IO Ground

Ground for the IO circuitry.

TDO

JTAG serial output

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the

 

Synchronous

JTAG feature is not being utilized, this pin can be left unconnected. This pin is not available

 

 

 

 

on TQFP packages.

 

 

 

TDI

JTAG serial input

Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature

 

Synchronous

is not being utilized, this pin can be left floating or connected to VDD through a pull up

 

 

 

 

resistor. This pin is not available on TQFP packages.

 

 

 

TMS

JTAG serial input

Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature

 

Synchronous

is not being utilized, this pin can be disconnected or connected to VDD. This pin is not

 

 

 

 

available on TQFP packages.

 

 

 

TCK

JTAG-

Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must

 

Clock

be connected to VSS. This pin is not available on TQFP packages.

NC

–

No connects. Not internally connected to the die. 36M, 72M, 144M, 288M, 576M, and 1G

 

 

 

 

are address expansion pins and are not internally connected to the die.

 

 

 

VSS/DNU

Ground/DNU

This pin can be connected to ground or can be left floating.

Functional Overview

All synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCDV) is 6.5 ns (133 MHz device).

The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F supports secondary cache in systems utilizing a linear or interleaved burst sequence. The interleaved burst order supports Pentium→ and i486™ processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with the processor address strobe (ADSP) or the controller address strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access.

Byte write operations are qualified with the byte write enable (BWE) and byte write select (BWX) inputs. A global write enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry.

Three synchronous chip selects (CE1, CE2, CE3 [2]) and an

asynchronous output enable (OE) provide for easy bank

selection and output tri-state control. ADSP is ignored if CE1 is HIGH.

Single Read Accesses

A single read access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 [2] are all

asserted active, and (2) ADSP or ADSC is asserted LOW (if the access is initiated by ADSC, the write inputs must be deasserted during this first cycle). The address presented to the address inputs is latched into the address register and the burst counter and/or control logic, and later presented to the memory core. If the OE input is asserted LOW, the requested data will be available at the data outputs with a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH.

Single Write Accesses Initiated by ADSP

This access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, CE3 [2] are all asserted active, and (2) ADSP is asserted LOW. The addresses presented are loaded into the address register and the burst inputs (GW, BWE, and BWX) are ignored during this first clock cycle. If the write inputs are asserted active (see Truth Table for Read/Write [4, 9] on page 10 for appropriate states that indicate a write) on the next clock rise, the appropriate data will be latched and written into the device. Byte writes are allowed. All IOs are tri-stated during a byte write. As this is a common IO device, the asynchronous OE input signal must be

Document #: 38-05544 Rev. *F

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Contents Cypress Semiconductor Corporation FeaturesSelection Guide 133 MHz 100 MHz UnitCY7C1381D, CY7C1381F CY7C1381D 512K x Pin Configurations Pin Tqfp Pinout 3 Chip EnableCY7C1383D 1M x Pin Configurations Pin Configurations Ball Fbga Pinout3 Chip Enable Name Description Pin DefinitionsByte write select inputs, active LOW. Qualified with Functional Overview = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics AddressCE1 CE2 CE3 Adsp Adsc ADV Write CLK Cycle Description UsedDQPC, Dqpa Truth Table for Read/Write 4Function CY7C1381D/CY7C1381F DQPB, DqpaTAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Bypass RegisterTAP Timing TAP AC Switching CharacteristicsParameter Description Conditions Min TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions 5V TAP AC Test ConditionsBit Size ×36 Bit Size ×18 Identification Register DefinitionsScan Register Sizes Identification CodesBit # Ball ID Ball BGA Boundary Scan Order 14A11 Ambient Range Electrical CharacteristicsMaximum Ratings Operating RangeThermal Resistance CapacitanceAC Test Loads and Waveforms 133 MHz 100 MHz Parameter Description Unit Min Switching CharacteristicsRead Cycle Timing Timing DiagramsAddress BWE Write Cycle Timing 26ADV Read/Write Cycle Timing 26, 28ZZ Mode Timing 30 Ordering Information Pin Thin Plastic Quad Flat pack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change

CY7C1381D, CY7C1381F, CY7C1383D, CY7C1383F specifications

The Cypress CY7C1383F, CY7C1383D, CY7C1381F, and CY7C1381D are high-performance static random-access memory (SRAM) devices designed for a variety of applications requiring fast data storage and retrieval. These memory chips are part of the Cypress SRAM family, known for their low power consumption, high speed, and data integrity, making them suitable for use in telecommunications, networking, and industrial applications.

One of the standout features of the CY7C1383F and CY7C1383D models is their high density, offering 256K bits of memory. This provides ample space for storing critical data while maintaining excellent performance. The CY7C1381F and CY7C1381D variants, having a smaller capacity of 128K bits, are ideal for applications where space and power savings are paramount. All four devices are organized as 32K x 8 bits, promoting ease of integration into various designs.

These SRAM devices utilize advanced CMOS technology, which not only enhances their speed but also reduces power consumption. The fast access times, reaching as low as 10 nanoseconds for the CY7C1383F and CY7C1381F, enable high-speed data processing, making these memories suitable for cache applications and high-speed buffering. Overall, their performance characteristics ensure data can be accessed quickly and efficiently.

The CY7C1383F and CY7C1383D models come with an extended temperature range, ensuring consistent performance even in harsh environments. This reliability is critical for industrial applications where fluctuating temperatures can affect device functionality. Moreover, the CY7C1381F and CY7C1381D share this advantage, making all four components suitable for different operating conditions.

Built-in features such as byte-wide write enable and chip enable signals significantly ease the control of data access and manipulation. Additionally, the asynchronous nature of these SRAM devices allows for simple interfacing with various microcontrollers and processors, facilitating integration into existing systems with minimal design modifications.

In summary, the Cypress CY7C1383F, CY7C1383D, CY7C1381F, and CY7C1381D SRAM devices deliver high-performance data storage solutions, characterized by low power consumption, fast access times, and reliability in diverse operating conditions. Their versatility makes them an excellent choice for engineers seeking robust memory solutions in their designs.
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