Cypress CY7C1383D Identification Register Definitions, Scan Register Sizes, Identification Codes

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CY7C1381D, CY7C1381F

 

 

 

 

 

 

 

 

 

 

CY7C1383D, CY7C1383F

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Identification Register Definitions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Instruction Field

 

 

 

 

CY7C1381D/CY7C1381F

CY7C1383D/CY7C1383F

 

Description

 

 

 

 

 

(512K × 36)

(1M × 18)

 

 

Revision Number (31:29)

 

 

 

 

000

 

000

 

Describes the version number.

 

 

 

 

 

 

 

 

 

 

 

 

 

Device Depth (28:24) [13]

 

 

 

 

01011

 

01011

 

Reserved for internal use.

Device Width (23:18) 119-BGA

 

101001

 

101001

 

Defines the memory type and

 

 

 

 

 

 

 

 

 

 

 

architecture.

Device Width (23:18) 165-FBGA

 

000001

 

000001

 

Defines the memory type and

 

 

 

 

 

 

 

 

 

 

 

architecture.

Cypress Device ID (17:12)

 

100101

 

010101

 

Defines the width and density.

 

 

 

 

 

 

 

 

 

 

Cypress JEDEC ID Code (11:1)

 

00000110100

00000110100

 

Allows unique identification of SRAM

 

 

 

 

 

 

 

 

 

 

 

vendor.

ID Register Presence Indicator (0)

 

1

 

1

 

Indicates the presence of an ID

 

 

 

 

 

 

 

 

 

 

 

register.

Scan Register Sizes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register Name

 

 

 

Bit Size (×36)

 

 

Bit Size (×18)

 

 

 

 

 

 

 

 

 

 

 

 

Instruction Bypass

 

 

 

 

 

 

 

3

 

 

3

 

 

 

 

 

 

 

 

 

 

 

 

Bypass

 

 

 

 

 

 

 

1

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

ID

 

 

 

 

 

 

 

32

 

 

32

 

 

 

 

 

 

 

Boundary Scan Order (119-ball BGA package)

 

85

 

 

85

 

 

 

 

 

 

 

Boundary Scan Order (165-ball fBGA package)

 

89

 

 

89

 

 

 

 

 

 

 

 

 

Identification Codes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Instruction

 

Code

 

 

 

Description

 

 

 

 

 

 

EXTEST

 

000

 

 

Captures Input/Output ring contents. Places the boundary scan register between TDI and

 

 

 

 

 

 

 

TDO. Forces all SRAM outputs to High-Z state.

 

 

 

IDCODE

 

001

 

 

Loads the ID register with the vendor ID code and places the register between TDI and TDO.

 

 

 

 

 

 

 

This operation does not affect SRAM operations.

 

 

 

SAMPLE Z

 

010

 

 

Captures Input/Output ring contents. Places the boundary scan register between TDI and

 

 

 

 

 

 

 

TDO. Forces all SRAM output drivers to a High-Z state.

RESERVED

 

011

 

 

Do Not Use. This instruction is reserved for future use.

 

 

 

 

 

 

SAMPLE/PRELOAD

 

100

 

 

Captures Input/Output ring contents. Places the boundary scan register between TDI and

 

 

 

 

 

 

 

TDO. Does not affect SRAM operation.

 

 

 

RESERVED

 

101

 

 

Do Not Use. This instruction is reserved for future use.

 

 

 

 

 

 

RESERVED

 

110

 

 

Do Not Use. This instruction is reserved for future use.

 

 

 

 

 

 

BYPASS

 

111

 

 

Places the bypass register between TDI and TDO. This operation does not affect SRAM

 

 

 

 

 

 

 

operations.

 

 

 

 

Note:

13. Bit #24 is “1” in the register definitions for both 2.5V and 3.3V versions of this device.

Document #: 38-05544 Rev. *F

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Contents Cypress Semiconductor Corporation FeaturesSelection Guide 133 MHz 100 MHz UnitCY7C1381D, CY7C1381F Pin Configurations Pin Tqfp Pinout 3 Chip Enable CY7C1381D 512K xCY7C1383D 1M x Pin Configurations Pin Configurations Ball Fbga Pinout3 Chip Enable Pin Definitions Name DescriptionByte write select inputs, active LOW. Qualified with Functional Overview = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics AddressCE1 CE2 CE3 Adsp Adsc ADV Write CLK Cycle Description UsedDQPC, Dqpa Truth Table for Read/Write 4Function CY7C1381D/CY7C1381F DQPB, DqpaTAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Bypass RegisterTAP Timing TAP AC Switching CharacteristicsParameter Description Conditions Min TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions 5V TAP AC Test ConditionsBit Size ×36 Bit Size ×18 Identification Register DefinitionsScan Register Sizes Identification CodesBit # Ball ID Ball BGA Boundary Scan Order 14A11 Ambient Range Electrical CharacteristicsMaximum Ratings Operating RangeCapacitance Thermal ResistanceAC Test Loads and Waveforms 133 MHz 100 MHz Parameter Description Unit Min Switching CharacteristicsRead Cycle Timing Timing DiagramsAddress BWE Write Cycle Timing 26ADV Read/Write Cycle Timing 26, 28ZZ Mode Timing 30 Ordering Information Pin Thin Plastic Quad Flat pack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change

CY7C1381D, CY7C1381F, CY7C1383D, CY7C1383F specifications

The Cypress CY7C1383F, CY7C1383D, CY7C1381F, and CY7C1381D are high-performance static random-access memory (SRAM) devices designed for a variety of applications requiring fast data storage and retrieval. These memory chips are part of the Cypress SRAM family, known for their low power consumption, high speed, and data integrity, making them suitable for use in telecommunications, networking, and industrial applications.

One of the standout features of the CY7C1383F and CY7C1383D models is their high density, offering 256K bits of memory. This provides ample space for storing critical data while maintaining excellent performance. The CY7C1381F and CY7C1381D variants, having a smaller capacity of 128K bits, are ideal for applications where space and power savings are paramount. All four devices are organized as 32K x 8 bits, promoting ease of integration into various designs.

These SRAM devices utilize advanced CMOS technology, which not only enhances their speed but also reduces power consumption. The fast access times, reaching as low as 10 nanoseconds for the CY7C1383F and CY7C1381F, enable high-speed data processing, making these memories suitable for cache applications and high-speed buffering. Overall, their performance characteristics ensure data can be accessed quickly and efficiently.

The CY7C1383F and CY7C1383D models come with an extended temperature range, ensuring consistent performance even in harsh environments. This reliability is critical for industrial applications where fluctuating temperatures can affect device functionality. Moreover, the CY7C1381F and CY7C1381D share this advantage, making all four components suitable for different operating conditions.

Built-in features such as byte-wide write enable and chip enable signals significantly ease the control of data access and manipulation. Additionally, the asynchronous nature of these SRAM devices allows for simple interfacing with various microcontrollers and processors, facilitating integration into existing systems with minimal design modifications.

In summary, the Cypress CY7C1383F, CY7C1383D, CY7C1381F, and CY7C1381D SRAM devices deliver high-performance data storage solutions, characterized by low power consumption, fast access times, and reliability in diverse operating conditions. Their versatility makes them an excellent choice for engineers seeking robust memory solutions in their designs.
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