Cypress CY7C1381D, CY7C1383F, CY7C1381F Document History, Issue Date Orig. Description of Change

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CY7C1381D, CY7C1381F

CY7C1383D, CY7C1383F

Document History Page

Document Title: CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Document Number: 38-05544

REV.

ECN NO.

Issue Date

Orig. of

Description of Change

Change

 

 

 

 

 

**

254518

See ECN

RKF

New data sheet

 

 

 

 

 

*A

288531

See ECN

SYT

Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for

 

 

 

 

non-compliance with 1149.1

 

 

 

 

Removed 117-MHz Speed Bin

 

 

 

 

Added Pb-free information for 100-Pin TQFP, 119 BGA and 165 FBGA

 

 

 

 

package

 

 

 

 

Added comment of ‘Pb-free BG packages availability’ below the Ordering Infor-

 

 

 

 

mation

*B

326078

See ECN

PCI

Address expansion pins/balls in the pinouts for all packages are modified as

 

 

 

 

per JEDEC standard

 

 

 

 

Added description on EXTEST Output Bus Tri-State

 

 

 

 

Changed description on the Tap Instruction Set Overview and Extest

 

 

 

 

Changed Device Width (23:18) for 119-BGA from 000001 to 101001

 

 

 

 

Added separate row for 165 -FBGA Device Width (23:18)

 

 

 

 

Changed ΘJA and ΘJC for TQFP Package from 31 and 6 °C/W to 28.66 and

 

 

 

 

4.08 °C/W respectively

 

 

 

 

Changed ΘJA and ΘJC for BGA Package from 45 and 7 °C/W to 23.8 and 6.2

 

 

 

 

°C/W respectively

 

 

 

 

Changed ΘJA and ΘJC for FBGA Package from 46 and 3 °C/W to 20.7 and 4.0

 

 

 

 

°C/W respectively

 

 

 

 

Modified VOL, VOH test conditions

 

 

 

 

Removed comment of ‘Pb-free BG packages availability’ below the Ordering

 

 

 

 

Information

 

 

 

 

Updated Ordering Information Table

 

 

 

 

Changed from Preliminary to Final

*C

351895

See ECN

PCI

Updated Ordering Information Table

 

 

 

 

 

*D

416321

See ECN

NXR

Changed address of Cypress Semiconductor Corporation on Page# 1 from

 

 

 

 

“3901 North First Street” to “198 Champion Court”

 

 

 

 

Changed the description of IX from Input Load Current to Input Leakage

 

 

 

 

Current on page# 18

 

 

 

 

Changed the IX current values of MODE on page # 18 from –5 A and 30 A

 

 

 

 

to –30 A and 5 A

 

 

 

 

Changed the IX current values of ZZ on page # 18 from –30 A and 5 A

 

 

 

 

to –5 A and 30 A

 

 

 

 

Changed VIH < VDD to VIH < VDDon page # 18

 

 

 

 

Replaced Package Name column with Package Diagram in the Ordering

 

 

 

 

Information table

 

 

 

 

Updated Ordering Information Table

*E

475009

See ECN

VKN

Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND

 

 

 

 

Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC

 

 

 

 

Switching Characteristics table.

 

 

 

 

Updated the Ordering Information table.

*F

776456

See ECN

VKN

Added Part numbers CY7C1381F and CY7C1383F and its related information

 

 

 

 

Added footnote# 3 regarding Chip Enable

 

 

 

 

Updated Ordering Information table

Document #: 38-05544 Rev. *F

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Contents Selection Guide Features133 MHz 100 MHz Unit Cypress Semiconductor CorporationCY7C1381D, CY7C1381F CY7C1383D 1M x Pin Configurations Pin Tqfp Pinout 3 Chip EnableCY7C1381D 512K x Pin Configurations Pin Configurations Ball Fbga Pinout3 Chip Enable Byte write select inputs, active LOW. Qualified with Pin DefinitionsName Description Functional Overview ZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDAddress = GNDCE1 CE2 CE3 Adsp Adsc ADV Write CLK Cycle Description UsedFunction CY7C1381D/CY7C1381F Truth Table for Read/Write 4DQPB, Dqpa DQPC, DqpaIeee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Controller Block Diagram TAP Instruction Set Bypass RegisterTAP Timing TAP AC Switching Characteristics3V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Parameter Description Conditions MinScan Register Sizes Identification Register DefinitionsIdentification Codes Bit Size ×36 Bit Size ×18Bit # Ball ID Ball BGA Boundary Scan Order 14A11 Maximum Ratings Electrical CharacteristicsOperating Range Ambient RangeAC Test Loads and Waveforms CapacitanceThermal Resistance 133 MHz 100 MHz Parameter Description Unit Min Switching CharacteristicsRead Cycle Timing Timing DiagramsAddress BWE Write Cycle Timing 26ADV Read/Write Cycle Timing 26, 28ZZ Mode Timing 30 Ordering Information Pin Thin Plastic Quad Flat pack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change

CY7C1381D, CY7C1381F, CY7C1383D, CY7C1383F specifications

The Cypress CY7C1383F, CY7C1383D, CY7C1381F, and CY7C1381D are high-performance static random-access memory (SRAM) devices designed for a variety of applications requiring fast data storage and retrieval. These memory chips are part of the Cypress SRAM family, known for their low power consumption, high speed, and data integrity, making them suitable for use in telecommunications, networking, and industrial applications.

One of the standout features of the CY7C1383F and CY7C1383D models is their high density, offering 256K bits of memory. This provides ample space for storing critical data while maintaining excellent performance. The CY7C1381F and CY7C1381D variants, having a smaller capacity of 128K bits, are ideal for applications where space and power savings are paramount. All four devices are organized as 32K x 8 bits, promoting ease of integration into various designs.

These SRAM devices utilize advanced CMOS technology, which not only enhances their speed but also reduces power consumption. The fast access times, reaching as low as 10 nanoseconds for the CY7C1383F and CY7C1381F, enable high-speed data processing, making these memories suitable for cache applications and high-speed buffering. Overall, their performance characteristics ensure data can be accessed quickly and efficiently.

The CY7C1383F and CY7C1383D models come with an extended temperature range, ensuring consistent performance even in harsh environments. This reliability is critical for industrial applications where fluctuating temperatures can affect device functionality. Moreover, the CY7C1381F and CY7C1381D share this advantage, making all four components suitable for different operating conditions.

Built-in features such as byte-wide write enable and chip enable signals significantly ease the control of data access and manipulation. Additionally, the asynchronous nature of these SRAM devices allows for simple interfacing with various microcontrollers and processors, facilitating integration into existing systems with minimal design modifications.

In summary, the Cypress CY7C1383F, CY7C1383D, CY7C1381F, and CY7C1381D SRAM devices deliver high-performance data storage solutions, characterized by low power consumption, fast access times, and reliability in diverse operating conditions. Their versatility makes them an excellent choice for engineers seeking robust memory solutions in their designs.