Cypress CY7C1356C, CY7C1354C manual Soldernotespad Type NON-SOLDER Mask Defined Nsmd

Page 27

CY7C1354C

CY7C1356C

Package Diagrams (continued)

165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D 165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180)

15.00±0.10

15.00±0.10

TOP VIEW

 

 

 

 

 

 

 

TOP VIEW

 

 

 

 

 

 

PIN 1 CORNER

 

 

 

 

 

 

 

 

 

 

 

 

 

PIN 1 CORNER

 

 

 

 

 

 

 

 

 

 

1

2

3

4

5

6

7

8

9

10

11

 

 

A

 

1

 

2

3

4

5

6

7

8

9

10

11

B

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CB

DC

ED

FE

GF

HG

JH

KJ

LK

ML

NM

PN

RP R

15.00±0.10

15.00±0.10

 

14.00

1.00

1.00

14.00

 

7.00

7.00

 

 

 

BOTTOM VIEW

 

 

 

 

 

 

 

 

 

 

 

 

BOTTOM VIEWPIN 1 CORNER

 

 

 

 

 

 

 

 

 

 

 

 

 

PIN 1 CORNER

 

 

 

 

 

 

Ø0.05 M C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ø0.05 M C

 

 

 

 

 

 

 

 

 

 

Ø0.25 M C A B

 

 

 

 

 

 

 

 

 

 

Ø0.50

-0Ø0.06

.25 M C A B

 

 

 

 

 

 

 

(165X)

 

 

 

 

 

 

 

 

 

 

 

 

 

+0.14

-0.06

 

 

 

11

10

9

8

7

6

5

Ø0.50

(165X)

 

4

3

2

1

 

 

 

 

 

 

 

 

 

 

 

 

+0.14

 

 

 

 

 

11

10

9

8

7

6

5

4

3

2

1A

BA

CB

DC

ED

FE

GF

HG

JH

KJ

LK

ML

NM

PN

RP

R

A

A

 

B

 

13.00±0.10

 

 

B

13.00±0.10

0.25 C

00.25.3±0C .05

0.53±0.05

 

 

 

C

SEATING PLANE

 

0.36

SEATING PLANE

 

0.36

C

A

1.40 MAX.

0.15 C 1.40MAX.

0.15C

 

 

 

 

 

 

0.35±0.06

0.35±0.06

 

1.00

A

5.00

1.00

 

5.00

 

10.00

 

10.00

B

13.00±0.10

B

13.00±0.10

0.15(4X)

 

0.15(4X)

 

NOTES :

 

SOLDERNOTESPAD TYPE: : NON-SOLDER MASK DEFINED (NSMD)

PACKAGESOLDERW IGHTPAD: 0TYPE.475g: NON-SOLDER MASK DEFINED (NSMD)

JEDEC REFERENCEPACKAGE WEIGHT: MO-216: 0./475gDESIGN 4.6C

PACKAGEJEDECODEREFERENCE: BB0AC : MO-216 / DESIGN 4.6C

PACKAGE CODE : BB0AC

51-85180-*A

51-85180-*A

NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders

Document #: 38-05538 Rev. *G

Page 27 of 28

© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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Image 27
Contents Cypress Semiconductor Corporation FeaturesLogic Block Diagram-CY7C1354C 256K x Functional Description1250 MHz 200 MHz 166 MHz Unit Logic Block Diagram-CY7C1356C 512K xMaximum Access Time Maximum Operating Current Selection Guide512K × Pin Configurations Pin Tqfp PinoutPin Configurations Ball BGA Pinout CY7C1354C 256K ×CY7C1356C 512K x CY7C1356C 512K × Pin Configurations Ball Fbga PinoutPin Definitions Functional Overview Single Read AccessesBurst Read Accesses Single Write AccessesInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Function CY7C1356C Sleep ModePartial Write Cycle Description2, 3, 4 Function CY7C1354CTAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Bypass RegisterSet-up Times TAP TimingParameter Description Min Max Unit Clock Output TimesIdentification Register Definitions TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions 5V TAP AC Test ConditionsInstruction Code Description Scan Register SizesIdentification Codes Register Name Bit SizeBit # Ball ID Boundary Scan Exit Order 256K ×K10 Boundary Scan Exit Order 512K ×B10 J10Ambient Range Electrical Characteristics Over the Operating Range14Maximum Ratings Operating Range3V I/O Test Load Capacitance16Thermal Resistance AC Test Loads and Waveforms250 200 166 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range 18A6 A7 ADV/LD BWXData Out DQNOP,STALL and Deselect Cycles23, 24 Switching WaveformsDON’T Care ZZ Mode Timing27Ordering Information CY7C1354C CY7C1356C Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package Diagrams90±0.05 Ball BGA 14 x 22 x 2.4 mmSoldernotespad Type NON-SOLDER Mask Defined Nsmd Document History ECN No Issue Date Orig. Description of Change