Cypress CY7C1356C, CY7C1354C manual 3V TAP AC Test Conditions, 5V TAP AC Test Conditions

Page 13

CY7C1354C

CY7C1356C

3.3V TAP AC Test Conditions

Input pulse levels

VSS to 3.3V

Input rise and fall times

1 ns

Input timing reference levels

1.5V

Output reference levels

1.5V

Test load termination supply voltage

1.5V

2.5V TAP AC Test Conditions

Input pulse levels

VSS to 2.5V

Input rise and fall time

1 ns

Input timing reference levels

1.25V

Output reference levels

1.25V

Test load termination supply voltage

1.25V

3.3V TAP AC Output Load Equivalent

2.5V TAP AC Output Load Equivalent

 

 

 

 

 

 

 

1.5V

 

 

 

 

 

 

 

 

 

1.25V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

50

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

50

 

TDO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TDO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ZO= 50

 

 

 

 

 

20pF

 

 

 

 

ZO= 50

 

 

 

 

 

 

 

 

20pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TAP DC Electrical Characteristics And Operating Conditions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(0°C < TA < +70°C; V = 3.3V ±0.165V unless otherwise noted)[12]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

 

 

Description

 

Test Conditions

 

 

Min.

 

 

 

 

 

Max.

Unit

VOH1

 

 

Output HIGH Voltage

IOH = –4.0 mA, VDDQ = 3.3V

 

 

2.4

 

 

 

 

 

 

 

 

 

 

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IOH = –1.0 mA, VDDQ = 2.5V

 

 

2.0

 

 

 

 

 

 

 

 

 

 

V

VOH2

 

 

Output HIGH Voltage

IOH = –100 µA

 

VDDQ = 3.3V

 

 

2.9

 

 

 

 

 

 

 

 

 

 

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDDQ = 2.5V

 

 

2.1

 

 

 

 

 

 

 

 

 

 

V

VOL1

 

 

Output LOW Voltage

 

IOL = 8.0 mA

 

VDDQ = 3.3V

 

 

 

 

 

0.4

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDDQ = 2.5V

 

 

 

 

 

0.4

V

VOL2

 

 

Output LOW Voltage

 

IOL = 100 µA

 

VDDQ = 3.3V

 

 

 

 

 

0.2

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDDQ = 2.5V

 

 

 

 

 

0.2

V

VIH

 

 

Input HIGH Voltage

 

 

 

VDDQ = 3.3V

 

 

2.0

 

 

VDD + 0.3

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDDQ = 2.5V

 

 

1.7

 

 

VDD + 0.3

V

VIL

 

 

Input LOW Voltage

 

 

 

VDDQ = 3.3V

 

 

–0.3

 

0.8

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDDQ = 2.5V

 

 

–0.3

 

0.7

V

IX

 

 

Input Load Current

 

GND < VIN < VDDQ

 

 

 

 

 

–5

 

5

µA

Identification Register Definitions

Instruction Field

CY7C1354C

CY7C1356C

Description

Revision Number (31:29)

000

000

Reserved for version number.

 

 

 

 

Cypress Device ID (28:12)[13]

01011001000100110

01011001000010110

Reserved for future use.

Cypress JEDEC ID (11:1)

00000110100

00000110100

Allows unique identification of SRAM vendor.

 

 

 

 

ID Register Presence (0)

1

1

Indicate the presence of an ID register.

 

 

 

 

Notes:

12.All voltages referenced to VSS (GND).

13.Bit #24 is “1” in the Register Definitions for both 2.5V and 3.3V versions of this device.

Document #: 38-05538 Rev. *G

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Contents Logic Block Diagram-CY7C1354C 256K x FeaturesFunctional Description1 Cypress Semiconductor CorporationMaximum Access Time Maximum Operating Current Logic Block Diagram-CY7C1356C 512K xSelection Guide 250 MHz 200 MHz 166 MHz Unit512K × Pin Configurations Pin Tqfp PinoutCY7C1354C 256K × Pin Configurations Ball BGA PinoutCY7C1356C 512K x CY7C1356C 512K × Pin Configurations Ball Fbga PinoutPin Definitions Burst Read Accesses Single Read AccessesSingle Write Accesses Functional OverviewLinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Partial Write Cycle Description2, 3, 4 Sleep ModeFunction CY7C1354C Function CY7C1356CTAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Bypass RegisterParameter Description Min Max Unit Clock TAP TimingOutput Times Set-up Times3V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Identification Register DefinitionsIdentification Codes Scan Register SizesRegister Name Bit Size Instruction Code DescriptionBit # Ball ID Boundary Scan Exit Order 256K ×B10 Boundary Scan Exit Order 512K ×J10 K10Maximum Ratings Electrical Characteristics Over the Operating Range14Operating Range Ambient RangeThermal Resistance Capacitance16AC Test Loads and Waveforms 3V I/O Test Load250 200 166 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range 18Data ADV/LD BWXOut DQ A6 A7NOP,STALL and Deselect Cycles23, 24 Switching WaveformsDON’T Care ZZ Mode Timing27Ordering Information CY7C1354C CY7C1356C Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package Diagrams90±0.05 Ball BGA 14 x 22 x 2.4 mmSoldernotespad Type NON-SOLDER Mask Defined Nsmd Document History ECN No Issue Date Orig. Description of Change