
CY7C1354C
CY7C1356C
3.3V TAP AC Test Conditions
Input pulse levels | VSS to 3.3V |
Input rise and fall times | 1 ns |
Input timing reference levels | 1.5V |
Output reference levels | 1.5V |
Test load termination supply voltage | 1.5V |
2.5V TAP AC Test Conditions
Input pulse levels | VSS to 2.5V |
Input rise and fall time | 1 ns |
Input timing reference levels | 1.25V |
Output reference levels | 1.25V |
Test load termination supply voltage | 1.25V |
3.3V TAP AC Output Load Equivalent | 2.5V TAP AC Output Load Equivalent |
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| 1.5V |
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| 1.25V |
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| 50Ω |
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| 50Ω |
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TDO |
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| TDO |
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| ZO= 50Ω |
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| 20pF |
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| ZO= 50Ω |
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| 20pF |
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TAP DC Electrical Characteristics And Operating Conditions |
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(0°C < TA < +70°C; V = 3.3V ±0.165V unless otherwise noted)[12] |
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| DD |
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Parameter |
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| Description |
| Test Conditions |
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| Min. |
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| Max. | Unit | |||||||||||||||||
VOH1 |
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| Output HIGH Voltage | IOH = |
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| 2.4 |
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| V | ||||||||||||||
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| IOH = |
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| 2.0 |
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| V | |||
VOH2 |
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| Output HIGH Voltage | IOH = |
| VDDQ = 3.3V |
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| 2.9 |
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| V | ||||||||||||
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| VDDQ = 2.5V |
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| 2.1 |
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| V | |
VOL1 |
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| Output LOW Voltage |
| IOL = 8.0 mA |
| VDDQ = 3.3V |
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| 0.4 | V | ||||||||||||||||||
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| VDDQ = 2.5V |
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| 0.4 | V | ||||||||
VOL2 |
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| Output LOW Voltage |
| IOL = 100 µA |
| VDDQ = 3.3V |
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| 0.2 | V | ||||||||||||||||||
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| VDDQ = 2.5V |
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| 0.2 | V | ||||||||
VIH |
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| Input HIGH Voltage |
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| VDDQ = 3.3V |
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| 2.0 |
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| VDD + 0.3 | V | ||||||||||||||||||
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| VDDQ = 2.5V |
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| 1.7 |
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| VDD + 0.3 | V | ||||||||
VIL |
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| Input LOW Voltage |
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| VDDQ = 3.3V |
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| 0.8 | V | ||||||||||||||||||||
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| VDDQ = 2.5V |
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| 0.7 | V | ||||||||||
IX |
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| Input Load Current |
| GND < VIN < VDDQ |
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| 5 | µA |
Identification Register Definitions
Instruction Field | CY7C1354C | CY7C1356C | Description |
Revision Number (31:29) | 000 | 000 | Reserved for version number. |
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Cypress Device ID (28:12)[13] | 01011001000100110 | 01011001000010110 | Reserved for future use. |
Cypress JEDEC ID (11:1) | 00000110100 | 00000110100 | Allows unique identification of SRAM vendor. |
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ID Register Presence (0) | 1 | 1 | Indicate the presence of an ID register. |
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Notes:
12.All voltages referenced to VSS (GND).
13.Bit #24 is “1” in the Register Definitions for both 2.5V and 3.3V versions of this device.
Document #: | Page 13 of 28 |
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