Cypress manual CY7C1354C CY7C1356C

Page 24

CY7C1354C

CY7C1356C

Ordering Information (continued)

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

250	CY7C1354C-250AXC	51-85050	100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free	Commercial
	CY7C1356C-250AXC

	CY7C1354C-250BGC	51-85115	119-ball Ball Grid Array (14 x 22 x 2.4 mm)

	CY7C1356C-250BGC

	CY7C1354C-250BGXC	51-85115	119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

	CY7C1356C-250BGXC

	CY7C1354C-250BZC	51-85180	165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

	CY7C1356C-250BZC

	CY7C1354C-250BZXC	51-85180	165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

	CY7C1356C-250BZXC

	CY7C1354C-250AXI	51-85050	100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free	Industrial

	CY7C1356C-250AXI

	CY7C1354C-250BGI	51-85115	119-ball Ball Grid Array (14 x 22 x 2.4 mm)

	CY7C1356C-250BGI

	CY7C1354C-250BGXI	51-85115	119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

	CY7C1356C-250BGXI

	CY7C1354C-250BZI	51-85180	165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

	CY7C1356C-250BZI

	CY7C1354C-250BZXI	51-85180	165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

	CY7C1356C-250BZXI

Document #: 38-05538 Rev. *G

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Contents Features Logic Block Diagram-CY7C1354C 256K xFunctional Description1 Cypress Semiconductor CorporationLogic Block Diagram-CY7C1356C 512K x Maximum Access Time Maximum Operating CurrentSelection Guide 250 MHz 200 MHz 166 MHz UnitPin Configurations Pin Tqfp Pinout 512K ×Pin Configurations Ball BGA Pinout CY7C1354C 256K ×CY7C1356C 512K x Pin Configurations Ball Fbga Pinout CY7C1356C 512K ×Pin Definitions Single Read Accesses Burst Read AccessesSingle Write Accesses Functional OverviewInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Sleep Mode Partial Write Cycle Description2, 3, 4Function CY7C1354C Function CY7C1356CTAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag Bypass Register TAP Instruction SetTAP Timing Parameter Description Min Max Unit ClockOutput Times Set-up TimesTAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test Conditions5V TAP AC Test Conditions Identification Register DefinitionsScan Register Sizes Identification CodesRegister Name Bit Size Instruction Code DescriptionBoundary Scan Exit Order 256K × Bit # Ball IDBoundary Scan Exit Order 512K × B10J10 K10Electrical Characteristics Over the Operating Range14 Maximum RatingsOperating Range Ambient RangeCapacitance16 Thermal ResistanceAC Test Loads and Waveforms 3V I/O Test LoadSwitching Characteristics Over the Operating Range 18 250 200 166 Parameter Description Unit Min MaxADV/LD BWX DataOut DQ A6 A7Switching Waveforms NOP,STALL and Deselect Cycles23, 24ZZ Mode Timing27 DON’T CareOrdering Information CY7C1354C CY7C1356C Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm 90±0.05Soldernotespad Type NON-SOLDER Mask Defined Nsmd ECN No Issue Date Orig. Description of Change Document History